autopep8 the whole thing

myhdl/_Cosimulation.py

@@ -48,7 +48,6 @@ class Cosimulation(object):
     """ Cosimulation class. """
 
     def __init__(self, exe="", **kwargs):
-
         """ Construct a cosimulation object. """
 
         if _simulator._cosim:

myhdl/_ShadowSignal.py

@@ -50,7 +50,6 @@ def next(self, val):
         raise AttributeError("ShadowSignals are readonly")
 
 
-
 class _SliceSignal(_ShadowSignal):
 
     __slots__ = ('_sig', '_left', '_right')
@@ -104,7 +103,6 @@ def _markUsed(self):
         self._used = True
         self._sig._used = True
 
-
     def toVerilog(self):
         if self._right is None:
             return "assign %s = %s[%s];" % (self._name, self._sig._name, self._left)
@@ -118,7 +116,6 @@ def toVHDL(self):
             return "%s <= %s(%s-1 downto %s);" % (self._name, self._sig._name, self._left, self._right)
 
 
-
 class ConcatSignal(_ShadowSignal):
 
     __slots__ = ('_args', '_sigargs', '_initval')
@@ -148,7 +145,7 @@ def __init__(self, *args):
                 w = len(a)
                 v = long(a, 2)
             else:
-                raise TypeError("ConcatSignal: inappropriate argument type: %s" \
+                raise TypeError("ConcatSignal: inappropriate argument type: %s"
                                 % type(a))
             nrbits += w
             val = val << w | v & (long(1) << w) - 1
@@ -209,12 +206,13 @@ def toVHDL(self):
                     else:
                         lines.append("%s(%s) <= %s(0);" % (self._name, lo, a._name))
                 else:
-                     lines.append("%s(%s) <= '%s';" % (self._name, lo, bin(ini[lo])))
+                    lines.append("%s(%s) <= '%s';" % (self._name, lo, bin(ini[lo])))
             else:
                 if isinstance(a, _Signal):
                     lines.append("%s(%s-1 downto %s) <= %s;" % (self._name, hi, lo, a._name))
                 else:
-                    lines.append('%s(%s-1 downto %s) <= "%s";' % (self._name, hi, lo, bin(ini[hi:lo], w)))
+                    lines.append('%s(%s-1 downto %s) <= "%s";' %
+                                 (self._name, hi, lo, bin(ini[hi:lo], w)))
             hi = lo
         return "\n".join(lines)
 
@@ -240,7 +238,8 @@ def toVerilog(self):
                 if isinstance(a, _Signal):
                     lines.append("assign %s[%s-1:%s] = %s;" % (self._name, hi, lo, a._name))
                 else:
-                    lines.append("assign %s[%s-1:%s] = 'b%s;" % (self._name, hi, lo, bin(ini[hi:lo], w)))
+                    lines.append("assign %s[%s-1:%s] = 'b%s;" %
+                                 (self._name, hi, lo, bin(ini[hi:lo], w)))
             hi = lo
         return "\n".join(lines)
 
@@ -301,7 +300,6 @@ def _resolve(self):
             self._next = res
             _siglist.append(self)
 
-
     def toVerilog(self):
         lines = []
         for d in self._drivers:
@@ -317,7 +315,6 @@ def toVHDL(self):
         return "\n".join(lines)
 
 
-
 class _TristateDriver(_Signal):
 
     __slots__ = ('_sig',)

myhdl/_Signal.py

@@ -63,18 +63,25 @@ def purge(self):
 
 
 class _PosedgeWaiterList(_WaiterList):
+
     def __init__(self, sig):
         self.sig = sig
+
     def _toVerilog(self):
         return "posedge %s" % self.sig._name
+
     def _toVHDL(self):
         return "rising_edge(%s)" % self.sig._name
 
+
 class _NegedgeWaiterList(_WaiterList):
+
     def __init__(self, sig):
         self.sig = sig
+
     def _toVerilog(self):
         return "negedge %s" % self.sig._name
+
     def _toVHDL(self):
         return "falling_edge(%s)" % self.sig._name
 
@@ -83,11 +90,14 @@ def posedge(sig):
     """ Return a posedge trigger object """
     return sig.posedge
 
+
 def negedge(sig):
     """ Return a negedge trigger object """
     return sig.negedge
 
 # signal factory function
+
+
 def Signal(val=None, delay=None):
     """ Return a new _Signal (default or delay 0) or DelayedSignal """
     if delay is not None:
@@ -97,6 +107,7 @@ def Signal(val=None, delay=None):
     else:
         return _Signal(val)
 
+
 class _Signal(object):
 
     """ _Signal class.
@@ -114,8 +125,7 @@ class _Signal(object):
                  '_driven', '_read', '_name', '_used', '_inList',
                  '_waiter', 'toVHDL', 'toVerilog', '_slicesigs',
                  '_numeric'
-                )
-
+                 )
 
     def __init__(self, val=None):
         """ Construct a signal.
@@ -211,8 +221,8 @@ def val(self):
     # support for the 'next' attribute
     @property
     def next(self):
-#        if self._next is self._val:
-#            self._next = deepcopy(self._val)
+        #        if self._next is self._val:
+        #            self._next = deepcopy(self._val)
         _siglist.append(self)
         return self._next
 
@@ -332,13 +342,11 @@ def __call__(self, left, right=None):
         self._slicesigs.append(s)
         return s
 
-
     ### operators for which delegation to current value is appropriate ###
 
     def __hash__(self):
         raise TypeError("Signals are unhashable")
 
-
     def __bool__(self):
         return bool(self._val)
 
@@ -361,6 +369,7 @@ def __add__(self, other):
             return self._val + other._val
         else:
             return self._val + other
+
     def __radd__(self, other):
         return other + self._val
 
@@ -369,6 +378,7 @@ def __sub__(self, other):
             return self._val - other._val
         else:
             return self._val - other
+
     def __rsub__(self, other):
         return other - self._val
 
@@ -377,6 +387,7 @@ def __mul__(self, other):
             return self._val * other._val
         else:
             return self._val * other
+
     def __rmul__(self, other):
         return other * self._val
 
@@ -385,6 +396,7 @@ def __truediv__(self, other):
             return self._val / other._val
         else:
             return self._val / other
+
     def __rtruediv__(self, other):
         return other / self._val
 
@@ -393,6 +405,7 @@ def __floordiv__(self, other):
             return self._val // other._val
         else:
             return self._val // other
+
     def __rfloordiv__(self, other):
         return other // self._val
 
@@ -401,6 +414,7 @@ def __mod__(self, other):
             return self._val % other._val
         else:
             return self._val % other
+
     def __rmod__(self, other):
         return other % self._val
 
@@ -411,6 +425,7 @@ def __pow__(self, other):
             return self._val ** other._val
         else:
             return self._val ** other
+
     def __rpow__(self, other):
         return other ** self._val
 
@@ -419,6 +434,7 @@ def __lshift__(self, other):
             return self._val << other._val
         else:
             return self._val << other
+
     def __rlshift__(self, other):
         return other << self._val
 
@@ -427,6 +443,7 @@ def __rshift__(self, other):
             return self._val >> other._val
         else:
             return self._val >> other
+
     def __rrshift__(self, other):
         return other >> self._val
 
@@ -435,6 +452,7 @@ def __and__(self, other):
             return self._val & other._val
         else:
             return self._val & other
+
     def __rand__(self, other):
         return other & self._val
 
@@ -443,6 +461,7 @@ def __or__(self, other):
             return self._val | other._val
         else:
             return self._val | other
+
     def __ror__(self, other):
         return other | self._val
 
@@ -451,6 +470,7 @@ def __xor__(self, other):
             return self._val ^ other._val
         else:
             return self._val ^ other
+
     def __rxor__(self, other):
         return other ^ self._val
 
@@ -486,22 +506,25 @@ def __hex__(self):
     def __index__(self):
         return int(self._val)
 
-
     # comparisons
     def __eq__(self, other):
         return self.val == other
+
     def __ne__(self, other):
         return self.val != other
+
     def __lt__(self, other):
         return self.val < other
+
     def __le__(self, other):
         return self.val <= other
+
     def __gt__(self, other):
         return self.val > other
+
     def __ge__(self, other):
         return self.val >= other
 
-
     # method lookup delegation
     def __getattr__(self, attr):
         return getattr(self._val, attr)
@@ -527,12 +550,10 @@ def _augm(self):
     __ior__ = __iand__ = __ixor__ = __irshift__ = __ilshift__ = _augm
     __itruediv__ = __ifloordiv__ = _augm
 
-
     # index and slice assignment not supported
     def __setitem__(self, key, val):
         raise TypeError("Signal object doesn't support item/slice assignment")
 
-
     # continues assignment support
     def assign(self, sig):
 
@@ -558,7 +579,7 @@ def toVerilog():
 class _DelayedSignal(_Signal):
 
     __slots__ = ('_nextZ', '_delay', '_timeStamp',
-                )
+                 )
 
     def __init__(self, val=None, delay=1):
         """ Construct a new DelayedSignal.
@@ -609,10 +630,12 @@ def delay(self, delay):
 
 
 class _SignalWrap(object):
+
     def __init__(self, sig, next, timeStamp):
         self.sig = sig
         self.next = next
         self.timeStamp = timeStamp
+
     def apply(self):
         return self.sig._apply(self.next, self.timeStamp)
 

myhdl/_Simulation.py

@@ -39,13 +39,16 @@
 
 schedule = _futureEvents.append
 
+
 class _error:
     pass
 _error.ArgType = "Inappriopriate argument type"
 _error.MultipleCosim = "Only a single cosimulator argument allowed"
 _error.DuplicatedArg = "Duplicated argument"
 
 # flatten Block objects out
+
+
 def _flatten(*args):
     arglist = []
     for arg in args:
@@ -60,6 +63,7 @@ def _flatten(*args):
 
 _error.MultipleSim = "Only a single Simulation instance is allowed"
 
+
 class Simulation(object):
 
     """ Simulation class.
@@ -89,7 +93,6 @@ def __init__(self, *args):
         del _futureEvents[:]
         del _siglist[:]
 
-
     def _finalize(self):
         cosim = self._cosim
         if cosim:
@@ -110,7 +113,6 @@ def quit(self):
         self._finalize()
 
     def run(self, duration=None, quiet=0):
-
         """ Run the simulation for some duration.
 
         duration -- specified simulation duration (default: forever)

myhdl/_Waiter.py

@@ -227,7 +227,6 @@ def _inferWaiter(gen):
     return _Waiter(gen)
 
 
-
 class _YieldVisitor(ast.NodeVisitor):
 
     def __init__(self, root):
@@ -286,7 +285,5 @@ def visit_Attribute(self, node):
             node.kind = _kind.EDGE
 
 
-
 # avoid problems with recursive imports
 from myhdl._instance import _Instantiator
-