Take this out. No idea what it was supposed to do.

myhdl/_extractHierarchy.py

@@ -49,16 +49,14 @@ class _error:
 
 
 class _Instance(object):
-    __slots__ = ['level', 'obj', 'subs', 'sigdict', 'memdict', 'name', 'func', 'argdict']
-    def __init__(self, level, obj, subs, sigdict, memdict, func, argdict):
+    __slots__ = ['level', 'obj', 'subs', 'sigdict', 'memdict', 'name']
+    def __init__(self, level, obj, subs, sigdict, memdict):
         self.level = level
         self.obj = obj
         self.subs = subs
         self.sigdict = sigdict
         self.memdict = memdict
-        self.func = func
-        self.argdict = argdict
-
+        self.name = None
 
 _memInfoMap = {}
 
@@ -307,11 +305,6 @@ def extractor(self, frame, event, arg):
                 if isGenSeq and arg:
                     sigdict = {}
                     memdict = {}
-                    argdict = {}
-                    if func:
-                        arglist = inspect.getargspec(func).args
-                    else:
-                        arglist = []
                     symdict = frame.f_globals.copy()
                     symdict.update(frame.f_locals)
                     cellvars = []
@@ -345,18 +338,14 @@ def extractor(self, frame, event, arg):
                             memdict[n] = m
                             if n in cellvars:
                                 m._used = True
-                        # save any other variable in argdict
-                        if (n in arglist) and (n not in sigdict) and (n not in memdict):
-                            argdict[n] = v
 
                     subs = []
                     for n, sub in frame.f_locals.items():
                         for elt in _inferArgs(arg):
                             if elt is sub:
                                 subs.append((n, sub))
 
-
-                    inst = _Instance(self.level, arg, subs, sigdict, memdict, func, argdict)
+                    inst = _Instance(self.level, arg, subs, sigdict, memdict)
                     self.hierarchy.append(inst)
 
                 self.level -= 1

myhdl/test/conversion/Makefile

@@ -3,13 +3,17 @@
 all: general toVerilog2 toVHDL toVerilog
 
 general:
-	cd general; make -k
+	cd general; py.test --sim ghdl; py.test --sim iverilog 
 
 toVerilog2:
-	cd toVerilog2; make -k
+	cd toVerilog2; py.test --sim iverilog 
 
 toVHDL:
-	cd toVHDL; make -k
+	cd toVHDL; py.test --sim ghdl 
 
 toVerilog: 
-	cd toVerilog; make -k 
+	cd toVerilog; py.test --sim iverilog 
+
+gitclean:
+	git clean -dfx    
+