Merge pull request #111 from jck/simulators

Various HDL simulator,  conversion test improvements

.gitignore

@@ -22,6 +22,7 @@ modelsim.ini
 transcript
 *.log
 work/
+work_nvc/
 work_vlog/
 work_vcom/
 *.wlf

.travis.yml

@@ -21,13 +21,13 @@ install:
 
 env:
   - CI_TARGET=core
-  - CI_TARGET=icarus
+  - CI_TARGET=iverilog
   - CI_TARGET=ghdl
 
 matrix:
   allow_failures:
     - python: "3.4"
-      env: CI_TARGET=icarus
+      env: CI_TARGET=iverilog
     - python: "3.4"
       env: CI_TARGET=ghdl
 

cosimulation/modelsim/Makefile

@@ -1,33 +1,25 @@
-# could add to CFLAGS to turn on warnings if you are using gcc
-WARNS=-Wall
+# This makefile assumes that 32bit Modelsim is installed.
+# If you have a 64 bit version, run 'ARCH=64 make'
+ARCH?=32
+CFLAGS_32= -m32
+CFLAGS_64= -m64
 
-# change this path to point to the pli include files directory for cver
+# Guess include dir based on location of vsim
 INCS=-I $(shell dirname `which vsim`)/../include
+CFLAGS= -Wall -shared -BSymbolic -fPIC $(CFLAGS_$(ARCH)) $(INCS)
 
-# maybe want -O<something> and/or -g
+VSIM_VERSION=$(shell vsim -version 2>/dev/null; echo $$?)
 
-# 32bit for Altera ASE/PE on Ubuntu Natty Narwhal
-CFLAGS= -fPIC -Wall -g -m32 $(INCS) -fno-stack-protector
-LFLAGS= -G -shared -export-dynamic -melf_i386
-
-# 64bit for SE
-#CFLAGS= -fPIC -Wall -c -g $(INCS)
-#LFLAGS= -shared -E
-
-# change to your compiler 
-CC=gcc 
 
 all: myhdl_vpi.so
 
-myhdl_vpi.o:	myhdl_vpi.c 
-	$(CC) $(CFLAGS) -c myhdl_vpi.c
-
-# make rules for dynamic libaries
-myhdl_vpi.so:	myhdl_vpi.o
-	$(LD) $(LFLAGS) myhdl_vpi.o -o myhdl_vpi.so
+myhdl_vpi.so: myhdl_vpi.c
+	$(info Compiling $(ARCH)bit vpi lib for "$(VSIM_VERSION)") 
+	$(info )
+	$(CC) $(CFLAGS) -o $@ $?
 
 clean:
-	-rm *.o *.so
+	@rm -f myhdl_vpi.so
 
 .PHONY: test
 test: myhdl_vpi.so

myhdl/_Cosimulation.py

@@ -27,8 +27,7 @@
 
 from myhdl._intbv import intbv
 from myhdl import _simulator, CosimulationError
-from myhdl._compat import string_types, to_bytes, to_str
-from myhdl._util import _setInheritable
+from myhdl._compat import set_inheritable, string_types, to_bytes, to_str
 
 _MAXLINE = 4096
 
@@ -60,12 +59,12 @@ def __init__(self, exe="", **kwargs):
         rf, wf = os.pipe()
 
         # Disable inheritance for ends that we don't want the child to have
-        _setInheritable(rt, False)
-        _setInheritable(wf, False)
+        set_inheritable(rt, False)
+        set_inheritable(wf, False)
 
         # Enable inheritance for child ends
-        _setInheritable(wt, True)
-        _setInheritable(rf, True)
+        set_inheritable(wt, True)
+        set_inheritable(rf, True)
 
         self._rt = rt
         self._wf = wf

myhdl/_compat.py

@@ -13,13 +13,15 @@
     class_types = (type,)
 
     from io import StringIO
+    from os import set_inheritable
     import builtins
 
     def to_bytes(s):
         return s.encode()
 
     def to_str(b):
         return b.decode()
+
 else:
     string_types = (str, unicode)
     integer_types = (int, long)
@@ -31,3 +33,30 @@ def to_str(b):
 
     to_bytes = _identity
     to_str = _identity
+
+    def set_inheritable(fd, inheritable):
+        # This implementation of set_inheritable is based on a code sample in
+        # [PEP 0446](https://www.python.org/dev/peps/pep-0446/) and on the
+        # CPython implementation of that proposal which can be browsed [here]
+        # (hg.python.org/releasing/3.4/file/8671f89107c8/Modules/posixmodule.c#l11130)
+        if sys.platform == "win32":
+            import msvcrt
+            import ctypes.windll.kernel32 as kernel32
+
+            HANDLE_FLAG_INHERIT = 1
+
+            if kernel32.SetHandleInformation(msvcrt.get_osfhandle(fd),
+                                             HANDLE_FLAG_INHERIT,
+                                             1 if inheritable else 0) == 0:
+                raise IOError("Failed on HANDLE_FLAG_INHERIT")
+        else:
+            import fcntl
+
+            fd_flags = fcntl.fcntl(fd, fcntl.F_GETFD)
+
+            if inheritable:
+                fd_flags &= ~fcntl.FD_CLOEXEC
+            else:
+                fd_flags |= fcntl.FD_CLOEXEC
+
+            fcntl.fcntl(fd, fcntl.F_SETFD, fd_flags)

myhdl/_util.py

@@ -92,33 +92,3 @@ def _genfunc(gen):
     else:
         func = gen.genfunc
     return func
-
-if hasattr(os, 'set_inheritable'):
-    _setInheritable = os.set_inheritable
-else:
-# This implementation of set_inheritable is based on a code sample in
-# [PEP 0446](https://www.python.org/dev/peps/pep-0446/) and on the
-# CPython implementation of that proposal which can be browsed [here]
-# (hg.python.org/releasing/3.4/file/8671f89107c8/Modules/posixmodule.c#l11130)
-    def _setInheritable(fd, inheritable):
-        if sys.platform == "win32":
-            import msvcrt
-            import ctypes.windll.kernel32 as kernel32
-
-            HANDLE_FLAG_INHERIT = 1
-
-            if kernel32.SetHandleInformation(msvcrt.get_osfhandle(fd),
-                                             HANDLE_FLAG_INHERIT,
-                                             1 if inheritable else 0) == 0:
-                raise IOError("Failed on HANDLE_FLAG_INHERIT")
-        else:
-            import fcntl
-
-            fd_flags = fcntl.fcntl(fd, fcntl.F_GETFD)
-
-            if inheritable:
-                fd_flags &= ~fcntl.FD_CLOEXEC
-            else:
-                fd_flags |= fcntl.FD_CLOEXEC
-
-            fcntl.fcntl(fd, fcntl.F_SETFD, fd_flags)

myhdl/conversion/_verify.py

@@ -6,6 +6,8 @@
 import subprocess
 import difflib
 
+from collections import namedtuple
+
 import myhdl
 from myhdl._Simulation import Simulation
 from myhdl.conversion._toVHDL import toVHDL
@@ -15,14 +17,10 @@
 # strip 'dev' for version
 _version = _version.replace('dev','')
 
-_simulators = []
-_hdlMap = {}
-_analyzeCommands = {}
-_elaborateCommands = {}
-_simulateCommands = {}
-_skiplinesMap = {}
-_skipcharsMap = {}
-_ignoreMap = {}
+_simulators = {}
+
+sim = namedtuple('sim', 'name hdl analyze elaborate simulate skiplines skipchars ignore')
+
 
 def registerSimulator(name=None, hdl=None, analyze=None, elaborate=None, simulate=None, 
                       skiplines=None, skipchars=None, ignore=None):
@@ -38,23 +36,23 @@ def registerSimulator(name=None, hdl=None, analyze=None, elaborate=None, simulat
             raise ValueError("Invalid elaborate command")
     if not isinstance(simulate, str) or (simulate.strip() == ""):
         raise ValueError("Invalid simulator command")
-    _simulators.append(name)
-    _hdlMap[name] = hdl
-    _analyzeCommands[name] = analyze
-    _elaborateCommands[name] = elaborate
-    _simulateCommands[name] = simulate
-    _skiplinesMap[name] = skiplines
-    _skipcharsMap[name] = skipchars
-    _ignoreMap[name] = ignore
+    _simulators[name] = sim(name, hdl, analyze, elaborate, simulate, skiplines, skipchars, ignore)
 
 registerSimulator(
-    name="GHDL",
+    name="ghdl",
     hdl="VHDL",
     analyze="ghdl -a --workdir=work pck_myhdl_%(version)s.vhd %(topname)s.vhd",
     elaborate="ghdl -e --workdir=work -o %(unitname)s %(topname)s",
     simulate="ghdl -r --workdir=work %(unitname)s"
     )
 
+registerSimulator(
+    name="nvc",
+    hdl="VHDL",
+    analyze="nvc --work=work_nvc -a pck_myhdl_%(version)s.vhd %(topname)s.vhd",
+    elaborate="nvc --work=work_nvc -e %(topname)s",
+    simulate="nvc --work=work_nvc -r %(topname)s"
+    )
 
 registerSimulator(
     name="vlog",
@@ -63,7 +61,7 @@ def registerSimulator(name=None, hdl=None, analyze=None, elaborate=None, simulat
     simulate='vsim work_vlog.%(topname)s -quiet -c -do "run -all; quit -f"',
     skiplines=6,
     skipchars=2,
-    ignore=("# **", "# run -all")
+    ignore=("# **", "# //", "# run -all")
     )
 
 registerSimulator(
@@ -73,12 +71,12 @@ def registerSimulator(name=None, hdl=None, analyze=None, elaborate=None, simulat
     simulate='vsim work_vcom.%(topname)s -quiet -c -do "run -all; quit -f"',
     skiplines=6,
     skipchars=2,
-    ignore=("# **", "#    Time:", "# run -all")
+    ignore=("# **", "# //", "#    Time:", "# run -all")
     )
 
 
 registerSimulator(
-    name="icarus",
+    name="iverilog",
     hdl="Verilog",
     analyze="iverilog -o %(topname)s.o %(topname)s.v",
     simulate="vvp %(topname)s.o"
@@ -104,12 +102,12 @@ def __init__(self, analyzeOnly=False):
 
     def __call__(self, func, *args, **kwargs):
 
-        hdlsim = self.simulator
-        if not hdlsim:
+        if not self.simulator:
             raise ValueError("No simulator specified")
-        if  not hdlsim in _simulators:
-            raise ValueError("Simulator %s is not registered" % hdlsim)
-        hdl = _hdlMap[hdlsim]
+        if  self.simulator not in _simulators:
+            raise ValueError("Simulator %s is not registered" % self.simulator)
+        hdlsim = _simulators[self.simulator]
+        hdl = hdlsim.hdl
         if hdl == 'Verilog' and toVerilog.name is not None:
             name = toVerilog.name
         elif hdl == 'VHDL' and toVHDL.name is not None:
@@ -122,14 +120,14 @@ def __call__(self, func, *args, **kwargs):
         vals['unitname'] = name.lower()
         vals['version'] = _version
 
-        analyze = _analyzeCommands[hdlsim] % vals
-        elaborate = _elaborateCommands[hdlsim]
+        analyze = hdlsim.analyze % vals
+        elaborate = hdlsim.elaborate
         if elaborate is not None:
             elaborate = elaborate % vals
-        simulate = _simulateCommands[hdlsim] % vals
-        skiplines = _skiplinesMap[hdlsim]
-        skipchars = _skipcharsMap[hdlsim]
-        ignore = _ignoreMap[hdlsim]
+        simulate = hdlsim.simulate % vals
+        skiplines = hdlsim.skiplines
+        skipchars = hdlsim.skipchars
+        ignore = hdlsim.ignore
 
         if hdl == "VHDL":
             inst = toVHDL(func, *args, **kwargs)
@@ -139,7 +137,7 @@ def __call__(self, func, *args, **kwargs):
         if hdl == "VHDL":
             if not os.path.exists("work"):
                 os.mkdir("work")
-        if hdlsim in ('vlog', 'vcom'):
+        if hdlsim.name in ('vlog', 'vcom'):
             if not os.path.exists("work_vsim"):
                 try:
                     subprocess.call("vlib work_vlog", shell=True)
@@ -201,10 +199,10 @@ def __call__(self, func, *args, **kwargs):
         glines = [line[skipchars:] for line in glines]
         flinesNorm = [line.lower() for line in flines]
         glinesNorm = [line.lower() for line in glines]
-        g = difflib.unified_diff(flinesNorm, glinesNorm, fromfile=hdlsim, tofile=hdl)
+        g = difflib.unified_diff(flinesNorm, glinesNorm, fromfile=hdlsim.name, tofile=hdl)
 
         MyHDLLog = "MyHDL.log"
-        HDLLog = hdlsim + ".log"
+        HDLLog = hdlsim.name + ".log"
         try:
             os.remove(MyHDLLog)
             os.remove(HDLLog)

myhdl/test/bugs/Makefile

@@ -2,20 +2,20 @@ all: vlog vcom
 
 
 vlog:
-	py.test vlog.py test_*.py
+	py.test --sim vlog
 
 vcom:
-	py.test vcom.py test_*.py
+	py.test --sim vcom
 
 
-GHDL:
-	py.test GHDL.py test_*.py
+ghdl:
+	py.test --sim ghdl
 
-icarus:
-	py.test icarus.py test_*.py
+iverilog:
+	py.test --sim iverilog
 
 cver:
-	py.test cver.py test_*.py
+	py.test --sim cver
 
 clean:
 	- rm *.o *.out *.v *.vhd *.pyc *~ *.vcd* *.log *_ghdl