Improve on large constant wires in VHDL

Triggered by an reported issue with Verilog that
I was not able to reproduce (issue 133).

myhdl/conversion/_toVHDL.py

@@ -473,9 +473,17 @@ def _convertGens(genlist, siglist, memlist, vfile):
             w = len(s)
             assert w != 0
             if s._min < 0:
-                pre, suf = "to_signed(", ", %s)" % w
+                if w <= 31:
+                    pre, suf = "to_signed(", ", %s)" % w
+                else:
+                    pre, suf = "signed'(", ")" 
+                    c = '"%s"' % bin(c, w)
             else:
-                pre, suf = "to_unsigned(", ", %s)" % w
+                if w <= 31:
+                    pre, suf = "to_unsigned(", ", %s)" % w
+                else:
+                    pre, suf = "unsigned'(", ")" 
+                    c = '"%s"' % bin(c, w)
         else:
             raise ToVHDLError("Unexpected type for constant signal", s._name)
         print("%s <= %s%s%s;" % (s._name, pre, c, suf), file=vfile)

myhdl/test/bugs/test_issue_133.py

@@ -0,0 +1,19 @@
+from __future__ import absolute_import
+from myhdl import *
+from myhdl.conversion import verify 
+
+def issue_133():
+    z = Signal(False)
+    large_signal = Signal(intbv(123456789123456, min=0, max=2**256))
+    @instance
+    def check():
+        z.next = large_signal[10]
+        yield delay(10)
+        print large_signal[31:] 
+        print large_signal[62:31] 
+        print large_signal[93:62] 
+
+    return check 
+
+def test_issue_133():
+    assert verify(issue_133) == 0