Factor visitor traversal out to top class

myhdl/_always_comb.py

@@ -32,8 +32,6 @@
 from myhdl._Waiter import _Waiter, _SignalWaiter, _SignalTupleWaiter
 from myhdl._instance import _Instantiator
 from myhdl._always import _Always
-from myhdl._resolverefs import _AttrRefTransformer
-from myhdl._visitors import _SigNameVisitor
 
 class _error:
     pass
@@ -91,20 +89,11 @@ def __init__(self, func):
         senslist = []
         super(_AlwaysComb, self).__init__(func, senslist)
 
-        tree = self.ast
-        # print ast.dump(tree)
-        v = _AttrRefTransformer(self)
-        v.visit(tree)
-        v = _SigNameVisitor(self.symdict)
-        v.visit(tree)
-        self.inputs = v.inputs
-        self.outputs = v.outputs
-
-        inouts = v.inouts | self.inputs.intersection(self.outputs)
+        inouts = self.inouts | self.inputs.intersection(self.outputs)
         if inouts:
             raise AlwaysCombError(_error.SignalAsInout % inouts)
 
-        if v.embedded_func:
+        if self.embedded_func:
             raise AlwaysCombError(_error.EmbeddedFunction)
 
         for n in self.inputs:

myhdl/_always_seq.py

@@ -32,8 +32,6 @@
 from myhdl._Signal import _Signal, _WaiterList,_isListOfSigs
 from myhdl._Waiter import _Waiter, _EdgeWaiter, _EdgeTupleWaiter
 from myhdl._always import _Always
-from myhdl._resolverefs import _AttrRefTransformer
-from myhdl._visitors import _SigNameVisitor
 
 # evacuate this later
 AlwaysSeqError = AlwaysError
@@ -101,23 +99,15 @@ def __init__(self, func, edge, reset):
 
         super(_AlwaysSeq, self).__init__(func, senslist)
 
-        # now infer outputs to be reset
-        tree = self.ast
-        # print ast.dump(tree)
-        v = _AttrRefTransformer(self)
-        v.visit(tree)
-        v = _SigNameVisitor(self.symdict)
-        v.visit(tree)
-
-        if v.inouts:
+        if self.inouts:
             raise AlwaysSeqError(_error.SigAugAssign, v.inouts)
 
-        if v.embedded_func:
+        if self.embedded_func:
             raise AlwaysSeqError(_error.EmbeddedFunction)
 
         sigregs = self.sigregs = []
         varregs = self.varregs = []
-        for n in v.outputs:
+        for n in self.outputs:
             reg = self.symdict[n]
             if isinstance(reg, _Signal):
                 sigregs.append(reg)

myhdl/_instance.py

@@ -26,6 +26,8 @@
 from myhdl import InstanceError
 from myhdl._util import _isGenFunc, _makeAST
 from myhdl._Waiter import _inferWaiter
+from myhdl._resolverefs import _AttrRefTransformer
+from myhdl._visitors import _SigNameVisitor
 
 class _error:
     pass
@@ -61,6 +63,17 @@ def __init__(self, genfunc):
             symdict.update(zip(freevars, closure))
         self.symdict = symdict
 
+        tree = self.ast
+        # print ast.dump(tree)
+        v = _AttrRefTransformer(self)
+        v.visit(tree)
+        v = _SigNameVisitor(self.symdict)
+        v.visit(tree)
+        self.inputs = v.inputs
+        self.outputs = v.outputs
+        self.inouts = v.inouts
+        self.embedded_func = v.embedded_func
+
     @property
     def funcobj(self):
         return self.genfunc

myhdl/_visitors.py

@@ -1,6 +1,6 @@
 import ast
 
-from myhdl import intbv
+from myhdl._intbv import intbv
 from myhdl._Signal import _Signal, _isListOfSigs