Merge pull request #92 from jck/0.9-release

0.9 docs update

doc/source/conf.py

@@ -13,10 +13,12 @@
 
 import sys, os
 
+
 # If extensions (or modules to document with autodoc) are in another directory,
 # add these directories to sys.path here. If the directory is relative to the
 # documentation root, use os.path.abspath to make it absolute, like shown here.
-#sys.path.insert(0, os.path.abspath('.'))
+sys.path.insert(0, os.path.abspath('../..'))
+import myhdl
 
 # -- General configuration -----------------------------------------------------
 
@@ -49,9 +51,9 @@
 # built documents.
 #
 # The short X.Y version.
-version = '0.8'
+# version = myhdl.__version__
 # The full version, including alpha/beta/rc tags.
-release = '0.8'
+release = myhdl.__version__
 
 # The language for content autogenerated by Sphinx. Refer to documentation
 # for a list of supported languages.

doc/source/index.rst

@@ -19,10 +19,18 @@ Welcome to the MyHDL documentation
 
    manual/index
    whatsnew/0.9
+   python3
+
+Old Whatsnew documents
+======================
+.. toctree::
+   :maxdepth: 1
+
    whatsnew/0.8
    whatsnew/0.7
    whatsnew/0.6
 
+
 Index
 =====
 
@@ -31,4 +39,3 @@ Index
 Search
 ======
 * :ref:`search`
-

doc/source/python3.rst

@@ -0,0 +1,8 @@
+Python 3 Support
+================
+
+MyHDL supports Python 3.4 and above.
+At the moment, core functions, cosimulation and Verilog conversion work perfectly.
+However, there are a few unresolved VHDL conversion bugs.
+
+All users are encouraged to try out their existing projects and tests with Python 3 and submit bug reports if anything goes wrong.

doc/source/whatsnew/0.4.rst

@@ -187,8 +187,11 @@ The following is a list of the statements that are supported by the
 Verilog converter, possibly qualified with restrictions or usage notes.
 
 The :keyword:`break` statement.
+
 The :keyword:`continue` statement.
+
 The :keyword:`def` statement.
+
 The :keyword:`for` statement.
     The only supported iteration scheme is iterating through sequences
     of integers returned by built-in function :func:`range` or
@@ -200,6 +203,7 @@ The :keyword:`if` statement.
     fully supported.
 
 The :keyword:`pass` statement.
+
 The :keyword:`print` statement.
     When printing an interpolated string, the format specifiers are
     copied verbatim to the Verilog output. Printing to a file (with
@@ -210,6 +214,7 @@ The :keyword:`raise` statement.
     simulation with an error message.
 
 The :keyword:`return` statement.
+
 The :keyword:`yield` statement.
     The yielded expression can be a signal, a signal edge as specified
     by MyHDL functions :func:`posedge` or :func:`negedge`, or a tuple of

doc/source/whatsnew/0.9.rst

@@ -6,8 +6,14 @@
 What's new in MyHDL 0.9
 ***********************
 
-Interfaces
-===========
+Python 3 Support
+================
+Experimental Python 3 support has been added to MyHDL 0.9
+
+See :doc:`/python3` for more info.
+
+Interfaces (Conversion of attribute accesses)
+=============================================
 
 Rationale
 ---------
@@ -20,7 +26,7 @@ errors.
 An *interface* is a collection of signals (:class:`Signal`)  embedded 
 in an class/object as attributes.  This provides a natural method 
 to group related signals and provides intuitive access through 
-attributes.  Multiple level of objects and attibutes provides a 
+attributes.  Multiple level of objects and attributes provides a 
 hierarchy of signal structure if desired.
 
 The following is an example of an *interface* definition::
@@ -31,15 +37,10 @@ The following is an example of an *interface* definition::
 	    self.imag = Signal(intbv(0, min=min, max=max))
 
 
-Previous versions supported *interfaces* for modeling and for 
-conversion if the attributes were locally referenced in a MyHDL 
-module outside of the `MyHDL generator`_.  If the attributes were 
-directly referenced in the `MyHDL generator`_ the code would not be 
-convertible.
-
-This features adds the ability to convert attributes that are 
-:class:`Signal` and referenced in the `MyHDL generator`_.  This is
-an evolution of a useful construct.  
+Although previous versions supported *interfaces* for modeling,
+`MyHDL generator`_\s which directly referenced attributes were not 
+convertible. 
+MyHDL now supports conversion of designs which contain attribute accesses.
 
 The following 
 is an example using the above ``Complex`` interface definition::
@@ -60,8 +61,8 @@ is an example using the above ``Complex`` interface definition::
 Solution
 --------
 The proposed solution is to create unique names for attributes which 
-are type :class:`Signal` and used by a `MyHDL generator`_.  The 
-converter will create a unique name by using the name of the parent 
+are used by `MyHDL generator`_\s.  The converter will create a unique 
+name by using the name of the parent 
 and the name of the attribute along with the name of the MyHDL module 
 instance (if required for uniqueness).  The converter will essentially 
 replace the "." with an "_" for each *interface* element.  
@@ -81,10 +82,8 @@ Conversion
 
 Limitations
 -----------
-The current implementation only converts ``Signal`` attributes and 
-constants (read-only ints).  Other Python structures will not be 
-analyzed (e.g. dict) and attributes used as variables will not be
-converted.
+Currently, MyHDL only converts interfaces in the form of attribute accesses.
+Dictionaries are not yet supported.