Merge pull request #130 from jck/py35

Python 3 fixes, test improvements
myhdl · Oct 7, 2015 · bd0cfba · bd0cfba
2 parents ddcc815 + ba99b90
commit bd0cfba
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Showing 50 changed files with 174 additions and 139 deletions.
diff --git a/.travis.yml b/.travis.yml
@@ -7,6 +7,7 @@ python:
   - "2.7"
   - "pypy"
   - "3.4"
+  - "3.5"
 
 addons:
   apt:
@@ -30,6 +31,10 @@ matrix:
       env: CI_TARGET=iverilog
     - python: "3.4"
       env: CI_TARGET=ghdl
+    - python: "3.5"
+      env: CI_TARGET=iverilog
+    - python: "3.5"
+      env: CI_TARGET=ghdl
 
 script: ./scripts/ci.sh
 

diff --git a/myhdl/_enum.py b/myhdl/_enum.py
@@ -85,6 +85,9 @@ def __repr__(self):
 
         __str__ = __repr__
 
+        def __int__(self):
+            return int(self._val, 2)
+
         def __hex__(self):
             return hex(int(self._val, 2))
 

diff --git a/myhdl/conversion/_analyze.py b/myhdl/conversion/_analyze.py
@@ -244,6 +244,12 @@ def visit_List(self, node):
         self.raiseError(node, _error.NotSupported, "list")
     def visitSliceObj(self, node):
         self.raiseError(node, _error.NotSupported, "slice object")
+
+    # All try blocks from python 3.3+
+    def visit_Try(self, node):
+        self.raiseError(node, _error.NotSupported, "try statement")
+
+    # Legacy try blocks
     def visit_TryExcept(self, node):
         self.raiseError(node, _error.NotSupported, "try-except statement")
     def visit_TryFinally(self, node):
@@ -257,11 +263,19 @@ def visit_Assign(self, node):
         self.visit(node.value)
 
     def visit_Call(self, node):
-        if node.starargs:
+        # ast.Call signature changed in python 3.5
+        # http://greentreesnakes.readthedocs.org/en/latest/nodes.html#Call
+        if sys.version_info >= (3, 5):
+            starargs = any(isinstance(arg, ast.Starred) for arg in node.args)
+            kwargs = any(kw.arg is None for kw in node.keywords)
+        else:
+            starargs = node.starargs is not None
+            kwargs = node.kwargs is not None
+
+        if starargs:
             self.raiseError(node, _error.NotSupported, "extra positional arguments")
-        if node.kwargs:
+        if kwargs:
             self.raiseError(node, _error.NotSupported, "extra named arguments")
-        # f = eval(_unparse(node.node), self.tree.symdict)
         self.generic_visit(node)
 
     def visit_Compare(self, node):

diff --git a/myhdl/test/__init__.py b/myhdl/test/__init__.py
diff --git a/myhdl/test/bugs/__init__.py b/myhdl/test/bugs/__init__.py
diff --git a/myhdl/test/conftest.py b/myhdl/test/conftest.py
@@ -1,3 +1,5 @@
+import sys
+
 import py
 import pytest
 
@@ -8,6 +10,9 @@
 
 all_sims = list(_simulators)
 
+if sys.version_info[0] > 2:
+    collect_ignore = ['conversion/toVerilog/test_not_supported_py2.py']
+
 def pytest_addoption(parser):
     parser.addoption("--sim", action="store", choices=all_sims,
                      help="HDL Simulator")

diff --git a/myhdl/test/conversion/general/__init__.py b/myhdl/test/conversion/general/__init__.py
diff --git a/myhdl/test/conversion/toVHDL/__init__.py b/myhdl/test/conversion/toVHDL/__init__.py
diff --git a/myhdl/test/conversion/toVHDL/test_custom.py b/myhdl/test/conversion/toVHDL/test_custom.py
@@ -215,15 +215,15 @@ def logic():
         expect = 0
         yield reset.posedge
         # assert count == expect
-        print count
+        print(count)
         while 1:
             yield clock.posedge
             if enable:
                 expect = (expect + 1) % n
             yield delay(1)
             # print "%d count %s expect %s count_v %s" % (now(), count, expect, count_v)
             # assert count == expect
-            print count
+            print(count)
     return logic
 
 

diff --git a/myhdl/test/conversion/toVHDL/test_enum.py b/myhdl/test/conversion/toVHDL/test_enum.py
@@ -40,23 +40,23 @@ def stimulus():
         a.next = 0xaa
         b.next = 0x55
         yield clock.posedge
-        print 'a=%s b=%s' % (a, b)
+        print('a=%s b=%s' % (a, b))
 
         op.next = bitwise_op.BW_AND
         yield clock.posedge
-        print c
+        print(c)
 
         op.next = bitwise_op.BW_ANDN
         yield clock.posedge
-        print c
+        print(c)
 
         op.next = bitwise_op.BW_OR
         yield clock.posedge
-        print c
+        print(c)
 
         op.next = bitwise_op.BW_XOR
         yield clock.posedge
-        print c
+        print(c)
 
         raise StopSimulation
 

diff --git a/myhdl/test/conversion/toVHDL/test_loops.py b/myhdl/test/conversion/toVHDL/test_loops.py
@@ -34,7 +34,7 @@ def stimulus():
         for i in range(100):
             a.next = data[i]
             yield delay(10)
-            print z
+            print(z)
 
     return stimulus, looptest_inst
 

diff --git a/myhdl/test/conversion/toVHDL/test_newcustom.py b/myhdl/test/conversion/toVHDL/test_newcustom.py
@@ -215,15 +215,15 @@ def logic():
         expect = 0
         yield reset.posedge
         # assert count == expect
-        print count
+        print(count)
         while 1:
             yield clock.posedge
             if enable:
                 expect = (expect + 1) % n
             yield delay(1)
             # print "%d count %s expect %s count_v %s" % (now(), count, expect, count_v)
             # assert count == expect
-            print count
+            print(count)
     return logic
 
 

diff --git a/myhdl/test/conversion/toVHDL/test_ops.py b/myhdl/test/conversion/toVHDL/test_ops.py
@@ -145,27 +145,27 @@ def check():
             yield left, right
             yield delay(1)
 
-            print Bitand
-            print Bitor
-            print Bitxor
-            print FloorDiv
-            print LeftShift
+            print(Bitand)
+            print(Bitor)
+            print(Bitxor)
+            print(FloorDiv)
+            print(LeftShift)
 
             # print Pow, Pow_v
 
-            print Modulo
-            print RightShift
-            print Mul
-            print Sub
-            print Sum
-            print int(EQ)
-            print int(NE)
-            print int(LT)
-            print int(GT)
-            print int(LE)
-            print int(GE)
-            print int(Booland)
-            print int(Boolor)
+            print(Modulo)
+            print(RightShift)
+            print(Mul)
+            print(Sub)
+            print(Sum)
+            print(int(EQ))
+            print(int(NE))
+            print(int(LT))
+            print(int(GT))
+            print(int(LE))
+            print(int(GE))
+            print(int(Booland))
+            print(int(Boolor))
 
     return binops, stimulus, check
 
@@ -253,11 +253,11 @@ def check():
             yield argm, argn, argp
             yield delay(1)
 
-            print Bitand
-            print Bitor
-            print Bitxor
-            print int(Booland)
-            print int(Boolor)
+            print(Bitand)
+            print(Bitor)
+            print(Bitxor)
+            print(int(Booland))
+            print(int(Boolor))
 
     return multiops, stimulus, check
 
@@ -315,8 +315,8 @@ def check():
         while 1:
             yield arg
             yield delay(1)
-            print int(Not_kw)
-            print Invert
+            print(int(Not_kw))
+            print(Invert)
             # check unary operator support in vhdl
             # print UnaryAdd
             # print UnarySub
@@ -449,16 +449,16 @@ def check():
         while True:
             yield left, right
             yield delay(1)
-            print Bitand
-            print Bitor
-            print Bitxor
-            print Sub
-            print Sum
-            print FloorDiv
-            print LeftShift
-            print Modulo
-            print Mul
-            print RightShift
+            print(Bitand)
+            print(Bitor)
+            print(Bitxor)
+            print(Sub)
+            print(Sum)
+            print(FloorDiv)
+            print(LeftShift)
+            print(Modulo)
+            print(Mul)
+            print(RightShift)
 
     return augmops, stimulus, check
 

diff --git a/myhdl/test/conversion/toVHDL/test_signed.py b/myhdl/test/conversion/toVHDL/test_signed.py
@@ -163,24 +163,24 @@ def check():
 ##                 self.assertEqual(Bitor, Bitor_v)
 ##                 self.assertEqual(Bitxor, Bitxor_v)
 ## ##                 self.assertEqual(FloorDiv, FloorDiv_v)
-            print LeftShift
+            print(LeftShift)
             # print Modulo
-            print Mul
+            print(Mul)
                 # self.assertEqual(Pow, Pow_v)
-            print RightShift
-            print Sub
-            print Sum
-            print Sum1
-            print Sum2
-            print Sum3
-            print int(EQ)
-            print int(NE)
-            print int(LT)
-            print int(GT)
-            print int(LE)
-            print int(GE)
-            print int(BoolAnd)
-            print int(BoolOr)
+            print(RightShift)
+            print(Sub)
+            print(Sum)
+            print(Sum1)
+            print(Sum2)
+            print(Sum3)
+            print(int(EQ))
+            print(int(NE))
+            print(int(LT))
+            print(int(GT))
+            print(int(LE))
+            print(int(GE))
+            print(int(BoolAnd))
+            print(int(BoolOr))
 
     return binops, stimulus, check
 
@@ -255,9 +255,9 @@ def check():
             yield arg
             yield delay(1)
             # print BoolNot
-            print Invert
+            print(Invert)
             # print UnaryAdd
-            print UnarySub
+            print(UnarySub)
 
 
     return unaryops, stimulus, check
@@ -399,12 +399,12 @@ def check():
 ##                 self.assertEqual(Bitor, Bitor_v)
 ##                 self.assertEqual(Bitxor, Bitxor_v)
 ##                 self.assertEqual(FloorDiv, FloorDiv_v)
-            print LeftShift
+            print(LeftShift)
 ##                 self.assertEqual(Modulo, Modulo_v)
-            print Mul
-            print RightShift
-            print Sub
-            print Sum
+            print(Mul)
+            print(RightShift)
+            print(Sub)
+            print(Sum)
 
     return augmops,  stimulus, check
 
@@ -488,8 +488,8 @@ def check():
         while 1:
             yield clk.posedge
             yield delay(1)
-            print int(a)
-            print int(b)
+            print(int(a))
+            print(int(b))
 
     @instance
     def clkgen():

diff --git a/myhdl/test/conversion/toVerilog/__init__.py b/myhdl/test/conversion/toVerilog/__init__.py
diff --git a/myhdl/test/conversion/toVerilog/test_GrayInc.py b/myhdl/test/conversion/toVerilog/test_GrayInc.py
@@ -6,10 +6,10 @@
 
 from myhdl import *
 
-from test_bin2gray import bin2gray
-from test_inc import inc
+from .test_bin2gray import bin2gray
+from .test_inc import inc
 
-from util import setupCosimulation
+from .util import setupCosimulation
 
 ACTIVE_LOW, INACTIVE_HIGH = 0, 1
 

diff --git a/myhdl/test/conversion/toVerilog/test_NotSupported.py b/myhdl/test/conversion/toVerilog/test_NotSupported.py
@@ -48,20 +48,6 @@ def logic():
             return logic
         self.check(g, z, a)
 
-    def testBackquote(self):
-        a = Signal(bool())
-        z = Signal(bool())
-        def g(z, a):
-            @instance
-            def logic():
-                while 1:
-                    yield a
-                    z.next = 1
-                    `a`
-            return logic
-        self.check(g, z, a)
-
-
     def testClass(self):
         a = Signal(bool())
         z = Signal(bool())
@@ -102,19 +88,6 @@ def logic():
             return logic
         self.check(g, z, a)
 
-    def testExec(self):
-        a = Signal(bool())
-        z = Signal(bool())
-        def g(z, a):
-            @instance
-            def logic():
-                while 1:
-                    yield a
-                    z.next = 1
-                    exec "1 + 2" in globals , locals
-            return logic
-        self.check(g, z, a)
-
     def testFrom(self):
         a = Signal(bool())
         z = Signal(bool())