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Fix #122 by removing support for named constant in VHDL
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jandecaluwe committed Sep 26, 2015
1 parent f10eb6d commit beed676
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Showing 2 changed files with 21 additions and 65 deletions.
6 changes: 0 additions & 6 deletions myhdl/conversion/_analyze.py
Original file line number Diff line number Diff line change
Expand Up @@ -52,9 +52,6 @@
builtinObjects = builtins.__dict__.values()

_enumTypeSet = set()
_constDict = {}
_extConstDict = {}


def _makeName(n, prefixes, namedict):
# trim empty prefixes
Expand Down Expand Up @@ -849,9 +846,6 @@ def getName(self, node):
self.tree.hasLos = True
elif isinstance(node.obj, int):
node.value = node.obj
# put VHDL compliant integer constants in global dict
if n not in _constDict and abs(node.obj) < 2**31:
_constDict[n] = node.obj
if n in self.tree.nonlocaldict:
# hack: put nonlocal intbv's in the vardict
self.tree.vardict[n] = v = node.obj
Expand Down
80 changes: 21 additions & 59 deletions myhdl/conversion/_toVHDL.py
Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,7 @@
from myhdl.conversion._misc import (_error,_kind,_context,
_ConversionMixin, _Label, _genUniqueSuffix, _isConstant)
from myhdl.conversion._analyze import (_analyzeSigs, _analyzeGens, _analyzeTopFunc,
_Ram, _Rom, _enumTypeSet, _constDict, _extConstDict)
_Ram, _Rom, _enumTypeSet)
from myhdl._Signal import _Signal,_WaiterList
from myhdl.conversion._toVHDLPackage import _package
from myhdl._util import _flatten
Expand Down Expand Up @@ -161,8 +161,6 @@ def __call__(self, func, *args, **kwargs):
_genUniqueSuffix.reset()
_enumTypeSet.clear()
_enumPortTypeSet.clear()
_constDict.clear()
_extConstDict.clear()

arglist = _flatten(h.top)
_checkArgs(arglist)
Expand Down Expand Up @@ -210,7 +208,6 @@ def __call__(self, func, *args, **kwargs):
_writeCustomPackage(vfile, intf)
_writeModuleHeader(vfile, intf, needPck, lib, arch, useClauses, doc, stdLogicPorts)
_writeFuncDecls(vfile)
_writeConstants(vfile)
_writeTypeDefs(vfile)
_writeSigDecls(vfile, intf, siglist, memlist)
_writeCompDecls(vfile, compDecls)
Expand Down Expand Up @@ -358,28 +355,6 @@ def _writeFuncDecls(f):
return
# print >> f, package

def _writeConstants(f):
f.write("\n")
# guess nice representation
for c in _constDict:
if c in _extConstDict:
continue
v = _constDict[c]
s = str(int(v))
sign = ''
if v < 0:
sign = '-'
for i in range(4, 31):
if abs(v) == 2**i:
s = "%s2**%s" % (sign, i)
break
if abs(v) == 2**i-1:
s = "%s2**%s-1" % (sign, i)
break
v = _constDict[c]
f.write("constant %s: integer := %s;\n" % (c, s))
f.write("\n")

def _writeTypeDefs(f):
f.write("\n")
sortedList = list(_enumTypeSet)
Expand Down Expand Up @@ -1319,40 +1294,27 @@ def getName(self, node):
obj = self.tree.symdict[n]
s = n
if isinstance(obj, bool):
s = "'%s'" % int(obj)
# print the symbol for a boolean in the global constant dict
if n in _constDict and obj == _constDict[n]:
if isinstance(node.vhd, vhd_boolean):
s = "bool(%s)" % n
elif isinstance(obj, integer_types):
# print the symbol for an integer in the global constant dict
if n in _constDict and obj == _constDict[n]:
assert abs(obj) < 2**31
if isinstance(node.vhd, vhd_int):
s = n
elif isinstance(node.vhd, vhd_boolean):
s = "bool(%s)" % n
elif isinstance(node.vhd, vhd_std_logic):
s = "stdl(%s)" % n
elif isinstance(node.vhd, vhd_unsigned):
s = "to_unsigned(%s, %s)" % (n, node.vhd.size)
elif isinstance(node.vhd, vhd_signed):
s = "to_signed(%s, %s)" % (n, node.vhd.size)
if isinstance(node.vhd, vhd_std_logic):
s = "'%s'" % int(obj)
else:
if isinstance(node.vhd, vhd_int):
s = self.IntRepr(obj)
elif isinstance(node.vhd, vhd_std_logic):
s = "'%s'" % int(obj)
elif isinstance(node.vhd, vhd_unsigned):
if abs(obj) < 2** 31:
s = "to_unsigned(%s, %s)" % (n, node.vhd.size)
else:
s = 'unsigned\'("%s")' % bin(obj, node.vhd.size)
elif isinstance(node.vhd, vhd_signed):
if abs(obj) < 2** 31:
s = "to_signed(%s, %s)" % (n, node.vhd.size)
else:
s = 'signed\'("%s")' % bin(obj, node.vhd.size)
s = "%s" % obj
elif isinstance(obj, integer_types):
if isinstance(node.vhd, vhd_int):
s = self.IntRepr(obj)
elif isinstance(node.vhd, vhd_boolean):
s = "%s" % bool(obj)
elif isinstance(node.vhd, vhd_std_logic):
s = "'%s'" % int(obj)
elif isinstance(node.vhd, vhd_unsigned):
if abs(obj) < 2** 31:
s = "to_unsigned(%s, %s)" % (obj, node.vhd.size)
else:
s = 'unsigned\'("%s")' % bin(obj, node.vhd.size)
elif isinstance(node.vhd, vhd_signed):
if abs(obj) < 2** 31:
s = "to_signed(%s, %s)" % (obj, node.vhd.size)
else:
s = 'signed\'("%s")' % bin(obj, node.vhd.size)
elif isinstance(obj, _Signal):
s = str(obj)
ori = inferVhdlObj(obj)
Expand Down

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