Merge pull request #115 from cfelton/verilog_inout

Added inout pot declaration to Verilog conversion for TristateSignals
myhdl · Jul 28, 2015 · c7d92c4 · c7d92c4
2 parents a1ba159 + 16bbf7e
commit c7d92c4
Showing 1 changed file with 4 additions and 1 deletion.
diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py
@@ -258,7 +258,10 @@ def _writeModuleHeader(f, intf, doc):
                     warnings.warn("%s: %s" % (_error.OutputPortRead, portname),
                                   category=ToVerilogWarning
                                   )
-            print("output %s%s%s;" % (p, r, portname), file=f)
+            if isinstance(s, _TristateSignal):
+                print("inout %s%s%s;" % (p, r, portname), file=f)
+            else:
+                print("output %s%s%s;" % (p, r, portname), file=f)
             if s._driven == 'reg':
                 print("reg %s%s%s;" % (p, r, portname), file=f)
             else: