Merge pull request #97 from cfelton/vhdl_delay

VHDL delay (wait) conversion fix
myhdl · Jul 11, 2015 · ebb7bcb · ebb7bcb
2 parents 7e3b071 + 67bc0b4
commit ebb7bcb
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
@@ -1006,7 +1006,7 @@ def visit_Call(self, node):
             self.write(f.__name__)
         elif f is delay:
             self.visit(node.args[0])
-            self.write(" ns")
+            self.write(" * 1 ns")
             return
         elif f is concat:
             pre, suf = self.inferCast(node.vhd, node.vhdOri)