Merge pull request #174 from josyb/WinCoSim

CoSimulation on Windows

myhdl/_Cosimulation.py

@@ -22,7 +22,7 @@
 
 import sys
 import os
-import shlex
+#import shlex
 import subprocess
 
 from myhdl._intbv import intbv
@@ -91,7 +91,9 @@ def __init__(self, exe="", **kwargs):
             env['MYHDL_FROM_PIPE'] = str(msvcrt.get_osfhandle(rf))
 
         if isinstance(exe, string_types):
-            exe = shlex.split(exe)
+#             exe = shlex.split(exe)
+            exe = exe.split(' ')
+
 
         try:
             sp = subprocess.Popen(exe, env=env, close_fds=False)

myhdl/_compat.py

@@ -1,4 +1,7 @@
-#pylint: disable=all
+''' 
+
+
+'''
 
 import sys
 import types
@@ -43,11 +46,14 @@ def set_inheritable(fd, inheritable):
         # (hg.python.org/releasing/3.4/file/8671f89107c8/Modules/posixmodule.c#l11130)
         if sys.platform == "win32":
             import msvcrt
-            import ctypes.windll.kernel32 as kernel32
+#             import ctypes.windll.kernel32 as kernel32
+            import ctypes
+            windll = ctypes.LibraryLoader(ctypes.WinDLL)
+            SetHandleInformation = windll.kernel32.SetHandleInformation
 
             HANDLE_FLAG_INHERIT = 1
 
-            if kernel32.SetHandleInformation(msvcrt.get_osfhandle(fd),
+            if SetHandleInformation(msvcrt.get_osfhandle(fd),
                                              HANDLE_FLAG_INHERIT,
                                              1 if inheritable else 0) == 0:
                 raise IOError("Failed on HANDLE_FLAG_INHERIT")

myhdl/conversion/_verify.py

@@ -69,7 +69,7 @@ def registerSimulator(name=None, hdl=None, analyze=None, elaborate=None, simulat
 registerSimulator(
     name="vcom",
     hdl="VHDL",
-    analyze="vcom -work work_vcom pck_myhdl_%(version)s.vhd %(topname)s.vhd",
+    analyze="vcom -2008 -work work_vcom pck_myhdl_%(version)s.vhd %(topname)s.vhd",
     simulate='vsim work_vcom.%(topname)s -quiet -c -do "run -all; quit -f"',
     skiplines=6,
     skipchars=2,

myhdl/test/core/test_Cosimulation.py

@@ -25,6 +25,9 @@
 import random
 import sys
 
+if sys.platform == "win32":
+    import msvcrt
+
 from myhdl import Signal
 from myhdl._compat import to_bytes
 from myhdl._Cosimulation import Cosimulation, CosimulationError, _error
@@ -56,6 +59,17 @@
 allSigs.update(toSigs)
 
 
+def wtrf():
+    if sys.platform != "win32":
+        wt = int(os.environ['MYHDL_TO_PIPE'])
+        rf = int(os.environ['MYHDL_FROM_PIPE'])
+    else:
+        wt = msvcrt.open_osfhandle(int(os.environ['MYHDL_TO_PIPE']), os.O_APPEND | os.O_TEXT)
+        rf = msvcrt.open_osfhandle(int(os.environ['MYHDL_FROM_PIPE']), os.O_RDONLY | os.O_TEXT)
+
+    return wt, rf
+
+
 class TestCosimulation:
 
     def setup_method(self, method):
@@ -72,8 +86,7 @@ def testNotUnique(self):
 
     @staticmethod
     def cosimNotUnique():
-        wt = int(os.environ['MYHDL_TO_PIPE'])
-        rf = int(os.environ['MYHDL_FROM_PIPE'])
+        wt, rf = wtrf()
         os.write(wt, b"TO 00 a 1")
         os.read(rf, MAXLINE)
         os.write(wt, b"FROM 00 d 1")
@@ -88,8 +101,7 @@ def testFromSignals(self):
 
     @staticmethod
     def cosimFromSignals():
-        wt = int(os.environ['MYHDL_TO_PIPE'])
-        rf = int(os.environ['MYHDL_FROM_PIPE'])
+        wt, rf = wtrf()
         buf = "FROM 00 "
         for s, w in zip(fromSignames, fromSizes):
             buf += "%s %s " % (s, w)
@@ -109,8 +121,7 @@ def testToSignals(self):
 
     @staticmethod
     def cosimToSignals():
-        wt = int(os.environ['MYHDL_TO_PIPE'])
-        rf = int(os.environ['MYHDL_FROM_PIPE'])
+        wt, rf = wtrf()
         buf = "TO 00 "
         for s, w in zip(toSignames, toSizes):
             buf += "%s %s " % (s, w)
@@ -130,8 +141,7 @@ def testFromToSignals(self):
 
     @staticmethod
     def cosimFromToSignals():
-        wt = int(os.environ['MYHDL_TO_PIPE'])
-        rf = int(os.environ['MYHDL_FROM_PIPE'])
+        wt, rf = wtrf()
         buf = "FROM 00 "
         for s, w in zip(fromSignames, fromSizes):
             buf += "%s %s " % (s, w)
@@ -151,8 +161,7 @@ def testTimeZero(self):
 
     @staticmethod
     def cosimTimeZero():
-        wt = int(os.environ['MYHDL_TO_PIPE'])
-        rf = int(os.environ['MYHDL_FROM_PIPE'])
+        wt, rf = wtrf()
         buf = "TO 01 "
         for s, w in zip(fromSignames, fromSizes):
             buf += "%s %s " % (s, w)
@@ -164,8 +173,7 @@ def testNoComm(self):
 
     @staticmethod
     def cosimNoComm():
-        wt = int(os.environ['MYHDL_TO_PIPE'])
-        rf = int(os.environ['MYHDL_FROM_PIPE'])
+        wt, rf = wtrf()
         os.write(wt, b"FROM 0000")
         os.read(rf, MAXLINE)
         os.write(wt, b"TO 0000")
@@ -179,8 +187,7 @@ def testFromSignalsDupl(self):
 
     @staticmethod
     def cosimFromSignalsDupl():
-        wt = int(os.environ['MYHDL_TO_PIPE'])
-        rf = int(os.environ['MYHDL_FROM_PIPE'])
+        wt, rf = wtrf()
         buf = "FROM 00 "
         for s, w in zip(fromSignames, fromSizes):
             buf += "%s %s " % (s, w)
@@ -193,8 +200,7 @@ def testToSignalsDupl(self):
 
     @staticmethod
     def cosimToSignalsDupl():
-        wt = int(os.environ['MYHDL_TO_PIPE'])
-        rf = int(os.environ['MYHDL_FROM_PIPE'])
+        wt, rf = wtrf()
         buf = "TO 00 "
         for s, w in zip(toSignames, toSizes):
             buf += "%s %s " % (s, w)
@@ -209,8 +215,7 @@ def testFromSignalVals(self):
 
     @staticmethod
     def cosimFromSignalVals():
-        wt = int(os.environ['MYHDL_TO_PIPE'])
-        rf = int(os.environ['MYHDL_FROM_PIPE'])
+        wt, rf = wtrf()
         buf = "FROM 00 "
         for s, w in zip(fromSignames, fromSizes):
             buf += "%s %s " % (s, w)
@@ -240,8 +245,7 @@ def testToSignalVals(self):
 
     @staticmethod
     def cosimToSignalVals():
-        wt = int(os.environ['MYHDL_TO_PIPE'])
-        rf = int(os.environ['MYHDL_FROM_PIPE'])
+        wt, rf = wtrf()
         buf = "FROM 00 "
         for s, w in zip(fromSignames, fromSizes):
             buf += "%s %s " % (s, w)