Use myhdldoctools instead of doctest

doc/source/myhdldoctools.py

@@ -22,7 +22,7 @@ def run(self):
         env = document.settings.env
         _ , wd = env.relfn2path(example_dir)
         prog = self.arguments[0]
-        out = subprocess.check_output(['python', '-u', prog], cwd=wd, 
+        out = subprocess.check_output(['python3', '-u', prog], cwd=wd, 
                                       stderr=subprocess.STDOUT,
                                       universal_newlines=True)
         out = '$ python {}\n{}'.format(prog, out)

example/manual/Hello.py

@@ -6,6 +6,6 @@ def Hello(clk, to="World!"):
 
     @always(clk.posedge)
     def say_hello():
-        print "%s Hello %s" % (now(), to)
+        print("%s Hello %s" % (now(), to))
 
     return say_hello

example/manual/conv_inc.py

@@ -0,0 +1,17 @@
+from myhdl import toVerilog, toVHDL, Signal, ResetSignal, modbv
+from inc import inc
+
+ACTIVE_LOW, INACTIVE_HIGH = 0, 1
+
+
+# conversion
+m = 8
+
+count = Signal(modbv(0)[m:])
+enable = Signal(bool(0))
+clock  = Signal(bool(0))
+reset = ResetSignal(0, active=0, async=True)
+
+inc_inst = inc(count, enable, clock, reset)
+inc_inst = toVerilog(inc, count, enable, clock, reset)
+inc_inst = toVHDL(inc, count, enable, clock, reset)

example/manual/fsm.py

@@ -1,95 +1,54 @@
-import myhdl
-from myhdl import *
+from myhdl import block, always_seq, Signal, intbv, enum
 
 ACTIVE_LOW = 0
 FRAME_SIZE = 8
-t_State = enum('SEARCH', 'CONFIRM', 'SYNC')
+t_state = enum('SEARCH', 'CONFIRM', 'SYNC')
 
 @block
-def FramerCtrl(SOF, state, syncFlag, clk, reset_n):
-    
+def framer_ctrl(sof, state, sync_flag, clk, reset_n):
+
     """ Framing control FSM.
 
-    SOF -- start-of-frame output bit
+    sof -- start-of-frame output bit
     state -- FramerState output
-    syncFlag -- sync pattern found indication input
+    sync_flag -- sync pattern found indication input
     clk -- clock input
     reset_n -- active low reset
-    
+
     """
-
-    index = Signal(0) # position in frame
 
-    @always(clk.posedge, reset_n.negedge)
+    index = Signal(intbv(0, min=0, max=FRAME_SIZE)) # position in frame
+
+    @always_seq(clk.posedge, reset=reset_n)
     def FSM():
         if reset_n == ACTIVE_LOW:
-            SOF.next = 0
+            sof.next = 0
             index.next = 0
-            state.next = t_State.SEARCH
+            state.next = t_state.SEARCH
 
         else:
             index.next = (index + 1) % FRAME_SIZE
-            SOF.next = 0
+            sof.next = 0
 
-            if state == t_State.SEARCH:
+            if state == t_state.SEARCH:
                 index.next = 1
-                if syncFlag:
-                    state.next = t_State.CONFIRM
+                if sync_flag:
+                    state.next = t_state.CONFIRM
 
-            elif state == t_State.CONFIRM:
+            elif state == t_state.CONFIRM:
                 if index == 0:
-                    if syncFlag:
-                        state.next = t_State.SYNC
+                    if sync_flag:
+                        state.next = t_state.SYNC
                     else:
-                        state.next = t_State.SEARCH
+                        state.next = t_state.SEARCH
 
-            elif state == t_State.SYNC:
+            elif state == t_state.SYNC:
                 if index == 0:
-                    if not syncFlag:
-                        state.next = t_State.SEARCH
-                SOF.next = (index == FRAME_SIZE-1)
+                    if not sync_flag:
+                        state.next = t_state.SEARCH
+                sof.next = (index == FRAME_SIZE-1)
 
             else:
                 raise ValueError("Undefined state")
 
     return FSM
-
-
-@block
-def testbench():
-
-    SOF = Signal(bool(0))
-    syncFlag = Signal(bool(0))
-    clk = Signal(bool(0))
-    reset_n = Signal(bool(1))
-    state = Signal(t_State.SEARCH)
-
-    framectrl = FramerCtrl(SOF, state, syncFlag, clk, reset_n)
-
-    @always(delay(10))
-    def clkgen():
-        clk.next = not clk
-
-    @instance
-    def stimulus():
-        for i in range(3):
-            yield clk.posedge
-        for n in (12, 8, 8, 4):
-            syncFlag.next = 1
-            yield clk.posedge
-            syncFlag.next = 0
-            for i in range(n-1):
-                yield clk.posedge
-        raise StopSimulation
-
-    return framectrl, clkgen, stimulus
-
-
-def main():
-    tb = testbench()
-    tb.config_sim(trace=True)
-    tb.run_sim()
-
-
-if __name__ == '__main__':
-    main()

example/manual/hello2.py

@@ -11,7 +11,7 @@ def drive_clk():
 
     @always(clk.posedge)
     def say_hello():
-        print "%s Hello World!" % now()
+        print("%s Hello World!" % now())
 
     return drive_clk, say_hello
 

example/manual/inc.py

@@ -1,92 +1,21 @@
-from random import randrange
-import myhdl
-from myhdl import *
+from myhdl import block, always_seq
 
-ACTIVE_LOW, INACTIVE_HIGH = 0, 1
+@block
+def inc(count, enable, clock, reset):
 
-def Inc(count, enable, clock, reset):
-
     """ Incrementer with enable.
-    
+
     count -- output
     enable -- control input, increment when 1
     clock -- clock input
     reset -- asynchronous reset input
     n -- counter max value
-    
+
     """
-    
+
     @always_seq(clock.posedge, reset=reset)
-    def incLogic():
+    def seq():
         if enable:
             count.next = count + 1
 
-    return incLogic
-
-
-def testbench():
-    m = 3
-    count = Signal(modbv(0)[m:])
-    enable = Signal(bool(0))
-    clock  = Signal(bool(0))
-    reset = ResetSignal(0, active=0, async=True)
-
-    inc_1 = Inc(count, enable, clock, reset)
-
-    HALF_PERIOD = delay(10)
-
-    @always(HALF_PERIOD)
-    def clockGen():
-        clock.next = not clock
-
-    @instance
-    def stimulus():
-        reset.next = ACTIVE_LOW
-        yield clock.negedge
-        reset.next = INACTIVE_HIGH
-        for i in range(20):
-            enable.next = min(1, randrange(3))
-            yield clock.negedge
-        raise StopSimulation
-
-    @instance
-    def monitor():
-        print "enable  count"
-        yield reset.posedge
-        while 1:
-            yield clock.posedge
-            yield delay(1)
-            print "   %s      %s" % (enable, count)
-
-    return clockGen, stimulus, inc_1, monitor
-
-tb = testbench()
-
-def main():
-    Simulation(tb).run()
-
-
-# conversion
-m = 8
-
-count = Signal(modbv(0)[m:])
-enable = Signal(bool(0))
-clock  = Signal(bool(0))
-reset = ResetSignal(0, active=0, async=True)
-
-inc_inst = Inc(count, enable, clock, reset)
-inc_inst = toVerilog(Inc, count, enable, clock, reset)
-inc_inst = toVHDL(Inc, count, enable, clock, reset)
-
-
-if __name__ == '__main__':
-    main()
-
-
-
-
-
-
-
-
-
+    return seq

example/manual/mux.py

@@ -1,34 +1,21 @@
-from myhdl import Signal, Simulation, delay
+from myhdl import block, always_comb, Signal
 
+@block
 def mux(z, a, b, sel):
+
     """ Multiplexer.
-    
+
     z -- mux output
     a, b -- data inputs
     sel -- control input: select a if asserted, otherwise b
+
     """
-    while 1:
-        yield a, b, sel
+
+    @always_comb
+    def comb():
         if sel == 1:
             z.next = a
         else:
             z.next = b
 
-from random import randrange
-
-(z, a, b, sel) = [Signal(0) for i in range(4)]
-
-MUX_1 = mux(z, a, b, sel)
-
-def test():
-    print "z a b sel"
-    for i in range(8):
-        a.next, b.next, sel.next = randrange(8), randrange(8), randrange(2)
-        yield delay(10)
-        print "%s %s %s %s" % (z, a, b, sel)
-
-def main():
-    Simulation(MUX_1, test()).run()    
-
-if __name__ == '__main__':
-    main()
+    return comb

example/manual/test_fsm.py

@@ -0,0 +1,38 @@
+import myhdl
+from myhdl import block, always, instance, Signal, ResetSignal, delay, StopSimulation
+from fsm import framer_ctrl, t_state
+
+ACTIVE_LOW = 0
+
+@block
+def testbench():
+
+    sof = Signal(bool(0))
+    sync_flag = Signal(bool(0))
+    clk = Signal(bool(0))
+    reset_n = ResetSignal(1, active=ACTIVE_LOW, async=True)
+    state = Signal(t_state.SEARCH)
+
+    frame_ctrl_0 = framer_ctrl(sof, state, sync_flag, clk, reset_n)
+
+    @always(delay(10))
+    def clkgen():
+        clk.next = not clk
+
+    @instance
+    def stimulus():
+        for i in range(3):
+            yield clk.negedge
+        for n in (12, 8, 8, 4):
+            sync_flag.next = 1
+            yield clk.negedge
+            sync_flag.next = 0
+            for i in range(n-1):
+                yield clk.negedge
+        raise StopSimulation()
+
+    return frame_ctrl_0, clkgen, stimulus
+
+tb = testbench()
+tb.config_sim(trace=True)
+tb.run_sim()

example/manual/test_inc.py

@@ -0,0 +1,49 @@
+import random
+from myhdl import block, always, instance, Signal, modbv, \
+                  ResetSignal, delay, StopSimulation
+from inc import inc
+
+random.seed(1)
+randrange = random.randrange
+
+ACTIVE_LOW, INACTIVE_HIGH = 0, 1
+
+@block
+def testbench():
+    m = 3
+    count = Signal(modbv(0)[m:])
+    enable = Signal(bool(0))
+    clock  = Signal(bool(0))
+    reset = ResetSignal(0, active=0, async=True)
+
+    inc_1 = inc(count, enable, clock, reset)
+
+    HALF_PERIOD = delay(10)
+
+    @always(HALF_PERIOD)
+    def clockGen():
+        clock.next = not clock
+
+    @instance
+    def stimulus():
+        reset.next = ACTIVE_LOW
+        yield clock.negedge
+        reset.next = INACTIVE_HIGH
+        for i in range(16):
+            enable.next = min(1, randrange(3))
+            yield clock.negedge
+        raise StopSimulation()
+
+    @instance
+    def monitor():
+        print("enable  count")
+        yield reset.posedge
+        while 1:
+            yield clock.posedge
+            yield delay(1)
+            print("   %s      %s" % (int(enable), count))
+
+    return clockGen, stimulus, inc_1, monitor
+
+tb = testbench()
+tb.run_sim()