Merge pull request #137 from nturley/master

fix bug in test_custom tests
myhdl · Nov 29, 2015 · fb70bb2 · fb70bb2
2 parents 480d228 + bb2ba3c
commit fb70bb2
Show file tree

Hide file tree

Showing 2 changed files with 12 additions and 12 deletions.
diff --git a/myhdl/test/conversion/toVHDL/test_custom.py b/myhdl/test/conversion/toVHDL/test_custom.py
@@ -74,10 +74,10 @@ def incProcess():
     __vhdl__ = \
 """
 process (%(clock)s, %(reset)s) begin
-    if (reset = '0') then
+    if (%(reset)s = '0') then
         %(count)s <= (others => '0');
     elsif rising_edge(%(clock)s) then
-        if (enable = '1') then
+        if (%(enable)s = '1') then
             %(count)s <= (%(count)s + 1) mod %(n)s;
         end if;
     end if;
@@ -104,11 +104,11 @@ def incProcess():
     __vhdl__ = \
 """
 always @(posedge %(clock)s, negedge %(reset)s) begin
-    if (reset == 0) begin
+    if (%(reset)s == 0) begin
         %(count)s <= 0;
     end
     else begin
-        if (enable) begin
+        if (%(enable)s) begin
             %(count)s <= (%(countq)s + 1) %% %(n)s;
         end
     end
@@ -151,10 +151,10 @@ def logic():
     __vhdl__ = \
 """
 process (%(clock)s, %(reset)s) begin
-    if (reset = '0') then
+    if (%(reset)s = '0') then
         %(count)s <= (others => '0');
     elsif rising_edge(%(clock)s) then
-        if (enable = '1') then
+        if (%(enable)s = '1') then
             %(count)s <= %(nextCount)s;
         end if;
     end if;

diff --git a/myhdl/test/conversion/toVHDL/test_newcustom.py b/myhdl/test/conversion/toVHDL/test_newcustom.py
@@ -74,10 +74,10 @@ def incProcess():
     inc.vhdl_code = \
 """
 process ($clock, $reset) begin
-    if (reset = '0') then
+    if ($reset = '0') then
         $count <= (others => '0');
     elsif rising_edge($clock) then
-        if (enable = '1') then
+        if ($enable = '1') then
             $count <= ($count + 1) mod $n;
         end if;
     end if;
@@ -104,11 +104,11 @@ def incProcess():
     incErr.vhdl_code = \
 """
 always @(posedge $clock, negedge $reset) begin
-    if (reset == 0) begin
+    if ($reset == 0) begin
         $count <= 0;
     end
     else begin
-        if (enable) begin
+        if ($enable) begin
             $count <= ($countq + 1) %% $n;
         end
     end
@@ -151,10 +151,10 @@ def logic():
     inc_seq.vhdl_code = \
 """
 process ($clock, $reset) begin
-    if (reset = '0') then
+    if ($reset = '0') then
         $count <= (others => '0');
     elsif rising_edge($clock) then
-        if (enable = '1') then
+        if ($enable = '1') then
             $count <= $nextCount;
         end if;
     end if;