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Changed DDR2 memory frequency to 125MHz
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vytautasb committed Jun 7, 2017
1 parent d157680 commit 54d8760
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Showing 10 changed files with 76 additions and 72 deletions.
10 changes: 5 additions & 5 deletions ip/ddr2/ddr2.vhd
View file
Expand Up @@ -316,14 +316,14 @@ END SYN;
-- Retrieval info: <PRIVATE name = "pipeline_commands" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "use_generated_memory_model" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "export_debug_port" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "local_if_clk_mhz_label" value="150.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "local_if_clk_mhz_label" value="125.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "pll_ref_clk_ps_label" value="(20000 ps)" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "pll_ref_clk_mhz" value="50.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_clk_mhz" value="150.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_clk_mhz" value="125.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "local_if_drate" value="Full" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "project_family" value="Cyclone IV GX" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_v72_rsu" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_clk_ps_label" value="(6667 ps)" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_clk_ps_label" value="(8000 ps)" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_memtype" value="DDR2 SDRAM" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "new_variant" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "family" value="Cyclone IV GX" type="STRING" enable="1" />
Expand All @@ -345,7 +345,7 @@ END SYN;
-- Retrieval info: <PRIVATE name = "mem_if_bankaddr_width" value="3" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_dq_per_dqs" value="8" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "vendor" value="Other" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_preset" value="alliance_AS4C64M16D2" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_preset" value="alliance_AS4C64M16D2_125MHz_v1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "fast_simulation_en" value="FAST" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_cs_width" value="1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_cs_per_dimm" value="1" type="STRING" enable="1" />
Expand Down Expand Up @@ -395,7 +395,7 @@ END SYN;
-- Retrieval info: <PRIVATE name = "mem_if_tmrd_ns" value="14.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tdsa_ps" value="50" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_twtr_ck" value="2" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_trtp_ns" value="7.5" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_trtp_ns" value="9.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_trcd_ns" value="12.5" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_drv_str" value="Normal" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tcl_50_fmax" value="400.0" type="STRING" enable="1" />
Expand Down
12 changes: 6 additions & 6 deletions ip/ddr2/ddr2_alt_mem_ddrx_controller_top.v
View file
Expand Up @@ -114,16 +114,16 @@ module ddr2_alt_mem_ddrx_controller_top(
localparam MEM_ADD_LAT = 0;
localparam MEM_TCL = 3;
localparam MEM_TRRD = 2;
localparam MEM_TFAW = 7;
localparam MEM_TRFC = 20;
localparam MEM_TREFI = 1170;
localparam MEM_TFAW = 6;
localparam MEM_TRFC = 16;
localparam MEM_TREFI = 975;
localparam MEM_TRCD = 2;
localparam MEM_TRP = 2;
localparam MEM_TWR = 3;
localparam MEM_TWR = 2;
localparam MEM_TWTR = 2;
localparam MEM_TRTP = 2;
localparam MEM_TRAS = 7;
localparam MEM_TRC = 9;
localparam MEM_TRAS = 6;
localparam MEM_TRC = 8;
localparam ADDR_ORDER = 0;
localparam MEM_AUTO_PD_CYCLES = 0;
localparam MEM_IF_RD_TO_WR_TURNAROUND_OCT = 3;
Expand Down
22 changes: 13 additions & 9 deletions ip/ddr2/ddr2_phy.vhd
View file
Expand Up @@ -216,13 +216,13 @@ BEGIN
MEM_IF_DQS_WIDTH => 2,
MEM_IF_OCT_EN => 0,
MEM_IF_CLK_PAIR_COUNT => 1,
MEM_IF_CLK_PS => 6667,
MEM_IF_CLK_PS_STR => "6667 ps",
MEM_IF_MR_0 => 1074,
MEM_IF_CLK_PS => 8000,
MEM_IF_CLK_PS_STR => "8000 ps",
MEM_IF_MR_0 => 562,
MEM_IF_MR_1 => 1092,
MEM_IF_MR_2 => 0,
MEM_IF_MR_3 => 0,
PLL_STEPS_PER_CYCLE => 64,
PLL_STEPS_PER_CYCLE => 80,
SCAN_CLK_DIVIDE_BY => 2,
MEM_IF_DQSN_EN => 0,
DLL_EXPORT_IMPORT => "EXPORT",
Expand Down Expand Up @@ -309,14 +309,14 @@ END SYN;
-- Retrieval info: <PRIVATE name = "pipeline_commands" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "use_generated_memory_model" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "export_debug_port" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "local_if_clk_mhz_label" value="150.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "local_if_clk_mhz_label" value="125.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "pll_ref_clk_ps_label" value="(20000 ps)" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "pll_ref_clk_mhz" value="50.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_clk_mhz" value="150.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_clk_mhz" value="125.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "local_if_drate" value="Full" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "project_family" value="Cyclone IV GX" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_v72_rsu" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_clk_ps_label" value="(6667 ps)" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_clk_ps_label" value="(8000 ps)" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_memtype" value="DDR2 SDRAM" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "new_variant" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "family" value="Cyclone IV GX" type="STRING" enable="1" />
Expand All @@ -338,7 +338,7 @@ END SYN;
-- Retrieval info: <PRIVATE name = "mem_if_bankaddr_width" value="3" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_dq_per_dqs" value="8" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "vendor" value="Other" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_preset" value="alliance_AS4C64M16D2" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_preset" value="alliance_AS4C64M16D2_125MHz_v1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "fast_simulation_en" value="FAST" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_cs_width" value="1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_cs_per_dimm" value="1" type="STRING" enable="1" />
Expand Down Expand Up @@ -388,7 +388,7 @@ END SYN;
-- Retrieval info: <PRIVATE name = "mem_if_tmrd_ns" value="14.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tdsa_ps" value="50" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_twtr_ck" value="2" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_trtp_ns" value="7.5" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_trtp_ns" value="9.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_trcd_ns" value="12.5" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_drv_str" value="Normal" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tcl_50_fmax" value="400.0" type="STRING" enable="1" />
Expand Down Expand Up @@ -522,6 +522,10 @@ END SYN;
-- Retrieval info: <PRIVATE name = "filename" value="ddr2_phy_syn.v" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "serializer"/>
-- Retrieval info: <NAMESPACE name = "quartus_settings">
-- Retrieval info: <PRIVATE name = "DEVICE" value="EP4CGX30CF23C7" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "FAMILY" value="Cyclone IV GX" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: </PRIVATES>
-- Retrieval info: <FILES/>
-- Retrieval info: <PORTS/>
Expand Down
2 changes: 1 addition & 1 deletion ip/ddr2/ddr2_phy_alt_mem_phy.v
View file
Expand Up @@ -2597,7 +2597,7 @@ endmodule
`include "alt_mem_phy_defines.v"

//DQS pin assignments
(* altera_attribute = " -name DQS_FREQUENCY 150.0MHz -to dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[0].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[1].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[2].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[3].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[4].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[5].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[6].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[7].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dm[0].dm_obuf -from dqs[0].dqs_obuf; -name DQS_FREQUENCY 150.0MHz -to dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[0].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[1].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[2].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[3].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[4].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[5].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[6].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[7].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dm[1].dm_obuf -from dqs[1].dqs_obuf" *)
(* altera_attribute = " -name DQS_FREQUENCY 125.0MHz -to dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[0].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[1].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[2].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[3].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[4].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[5].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[6].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[7].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dm[0].dm_obuf -from dqs[0].dqs_obuf; -name DQS_FREQUENCY 125.0MHz -to dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[0].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[1].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[2].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[3].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[4].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[5].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[6].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[7].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dm[1].dm_obuf -from dqs[1].dqs_obuf" *)

//
module ddr2_phy_alt_mem_phy_dp_io (
Expand Down
70 changes: 35 additions & 35 deletions ip/ddr2/ddr2_phy_alt_mem_phy_pll.vhd
View file
Expand Up @@ -187,25 +187,25 @@ BEGIN
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_divide_by => 4,
clk0_duty_cycle => 50,
clk0_multiply_by => 3,
clk0_multiply_by => 5,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_divide_by => 2,
clk1_duty_cycle => 50,
clk1_multiply_by => 3,
clk1_multiply_by => 5,
clk1_phase_shift => "0",
clk2_divide_by => 1,
clk2_divide_by => 2,
clk2_duty_cycle => 50,
clk2_multiply_by => 3,
clk2_phase_shift => "-1667",
clk3_divide_by => 1,
clk2_multiply_by => 5,
clk2_phase_shift => "-2000",
clk3_divide_by => 2,
clk3_duty_cycle => 50,
clk3_multiply_by => 3,
clk3_multiply_by => 5,
clk3_phase_shift => "0",
clk4_divide_by => 1,
clk4_divide_by => 2,
clk4_duty_cycle => 50,
clk4_multiply_by => 3,
clk4_multiply_by => 5,
clk4_phase_shift => "0",
compensate_clock => "CLK1",
inclk0_input_frequency => 20000,
Expand Down Expand Up @@ -256,7 +256,7 @@ BEGIN
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
vco_frequency_control => "MANUAL_PHASE",
vco_phase_shift_step => 104,
vco_phase_shift_step => 100,
width_clock => 5,
width_phasecounterselect => 3
)
Expand Down Expand Up @@ -305,11 +305,11 @@ END SYN;
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "75.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "150.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "150.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "150.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "150.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "62.500000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "125.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "125.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "125.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
Expand All @@ -334,7 +334,7 @@ END SYN;
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "deg"
-- Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_EDIT STRING "104.00000000"
-- Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_EDIT STRING "100.00000000"
-- Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_UNIT STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
Expand All @@ -348,11 +348,11 @@ END SYN;
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "75.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "150.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "150.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "150.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "150.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "62.50000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "125.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "125.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "125.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "125.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
Expand Down Expand Up @@ -419,25 +419,25 @@ END SYN;
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1667"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-2000"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
Expand Down Expand Up @@ -488,7 +488,7 @@ END SYN;
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: VCO_FREQUENCY_CONTROL STRING "MANUAL_PHASE"
-- Retrieval info: CONSTANT: VCO_PHASE_SHIFT_STEP NUMERIC "104"
-- Retrieval info: CONSTANT: VCO_PHASE_SHIFT_STEP NUMERIC "100"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_PHASECOUNTERSELECT NUMERIC "3"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
Expand Down
8 changes: 4 additions & 4 deletions ip/ddr2/ddr2_phy_alt_mem_phy_seq_wrapper.v
View file
Expand Up @@ -103,12 +103,12 @@ module ddr2_phy_alt_mem_phy_seq_wrapper (
localparam DBG_A_WIDTH = 13;
localparam DQS_PHASE_SETTING = 2;
localparam SCAN_CLK_DIVIDE_BY = 2;
localparam PLL_STEPS_PER_CYCLE = 64;
localparam MEM_IF_CLK_PS = 6667;
localparam PLL_STEPS_PER_CYCLE = 80;
localparam MEM_IF_CLK_PS = 8000;
localparam DQS_DELAY_CTL_WIDTH = 6;
localparam MEM_IF_MEMTYPE = "DDR2";
localparam RANK_HAS_ADDR_SWAP = 0;
localparam MEM_IF_MR_0 = 1074;
localparam MEM_IF_MR_0 = 562;
localparam MEM_IF_MR_1 = 1092;
localparam MEM_IF_MR_2 = 0;
localparam MEM_IF_MR_3 = 0;
Expand All @@ -134,7 +134,7 @@ module ddr2_phy_alt_mem_phy_seq_wrapper (
localparam FORCE_HC = 0;
localparam MEM_IF_DQS_CAPTURE_EN = 0;
localparam REDUCE_SIM_TIME = 0;
localparam TINIT_TCK = 30004;
localparam TINIT_TCK = 25000;
localparam TINIT_RST = 0;
localparam GENERATE_ADDITIONAL_DBG_RTL = 0;
localparam MEM_IF_CS_PER_RANK = 1;
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