Altera Cyclone IV FPGA project for the USB 3.0 LimeSDR board
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.qsys_edit Modified Avfifo module to 32b size Oct 18, 2016
.settings File cleanup Oct 28, 2016
ip Merge branch lml_modes Dec 11, 2017
lms_ctr File cleanup Oct 28, 2016
output_files Recompiled project Jun 7, 2018
signal_tap Recompiled project May 30, 2018
software Ver. 2.8. NIOS CMD_GPIO_WR byte swap Mar 30, 2017
src Added automatic reset for TX packet loss flag Jun 7, 2018
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.project File cleanup Oct 28, 2016
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Av_FIFO_Int_hw.tcl~ File cleanup Oct 28, 2016
COPYING Update COPYING Nov 8, 2016
Clock_groups.sdc Modified SDC files May 18, 2018
DDR2_1_pin_assigments_v01.tcl Ver. 13. WFM player feature Jun 28, 2016
FX3_timing.sdc Recompiled project Dec 1, 2017
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LimeSDR-USB_lms7_trx.qsf Recompiled project Jun 7, 2018
LimeSDR-USB_lms7_trx_assignment_defaults.qdf Added NIOS CPU core Oct 10, 2016
README.md README.md Update Dec 20, 2016
User_timing_reports.tcl Ver. 16. Rx path mod for packet skipping Sep 13, 2016
assignment_defaults.qdf Initial commit Apr 8, 2016
gen_prg_files.tcl Test pattern for tx path Feb 14, 2017
gui.tcl Ver. 16. Rx path mod for packet skipping Sep 13, 2016
lms7_trx.qpf Initial commit Apr 8, 2016
lms7_trx_timing.sdc Modified SDC files May 18, 2018
lms7_trx_top.bdf Recompiled project May 18, 2018
lms_ctr.qsys LMS SPI clk 16MHz, GPIF busy indication, NIOS R/W word 4 bytes Oct 18, 2016
lms_ctr.sopcinfo Modified Avfifo module to 32b size Oct 18, 2016
update_rev.tcl Ver. 16. Rx path mod for packet skipping Sep 13, 2016

README.md

LimeSDR-USB FPGA gateware

This repository contains the FPGA gateware project for the USB 3.0 LimeSDR board.

The gateware can be built with the free version of the Altera Quartus tools.

Branches

This repository contains the following hardware-specific branches:

  • master:

    • Compiled gateware file for Hardware Revision 1v4 is output_files/LimeSDR-USB_lms7_trx_HW_1.4.rbf.
  • HW_v1.3-v1.0:

    • Compiled gateware file for Hardware Revision 1v3 is output_files/LimeSDR-USB_lms7_trx_HW_1.3.rbf.
    • Compiled gateware file for Hardware Revision 1v2 is output_files/LimeSDR-USB_lms7_trx_HW_1.2.rbf.
    • Compiled gateware file for Hardware Revision 1v1 is output_files/LimeSDR-USB_lms7_trx_HW_1.1.rbf.
    • Compiled gateware file for Hardware Revision 1v0 is output_files/LimeSDR-USB_lms7_trx_HW_1.0.rbf.

Licensing

Please see the COPYING file(s). However, please note that the license terms stated do not extend to any files provided with the Altera design tools and see the relevant files for the associated terms and conditions.