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Ver.2.17. Merge branch master_clean
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@vbuitvydas
vbuitvydas committed Jun 5, 2018
2 parents 91f07ec + 429bb02 commit 4f2bc44
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Showing 99 changed files with 41,022 additions and 41,508 deletions.
28 changes: 28 additions & 0 deletions Clock_groups.sdc
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@@ -0,0 +1,28 @@
################################################################################
#Asyncronous clocks
################################################################################
# To clocks that are not related to each other
set_clock_groups -asynchronous -group {SI_CLK0} \
-group {SI_CLK1} \
-group {SI_CLK2} \
-group {SI_CLK3} \
-group {SI_CLK5} \
-group {SI_CLK6} \
-group {SI_CLK7} \
-group {LMK_CLK} \
-group {BRDG_SPI_SCLK} \
-group {LMS_MCLK1} \
-group {LMS_MCLK1_5MHZ} \
-group {TX_PLLCLK_C0 } \
-group {TX_PLLCLK_C1 LMS_FCLK1_PLL} \
-group {LMS_FCLK1_DRCT } \
-group {LMS_MCLK2} \
-group {LMS_MCLK2_5MHZ} \
-group {RX_PLLCLK_C0} \
-group {RX_PLLCLK_C1 } \
-group {LMS_FCLK2_PLL} \
-group {LMS_FCLK2_DRCT } \
-group {FX3_PCLK FPGA_SPI0_SCLK_reg FPGA_SPI0_SCLK_out} \
-group {*|wfm_player_top_inst2|DDR2_ctrl_top_inst|ddr2_inst|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1]} \
-group {*|ddr2_tester_inst2|ddr2_inst|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1]}

312 changes: 294 additions & 18 deletions LimeSDR-USB_lms7_trx.qsf
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70 changes: 18 additions & 52 deletions lms7_trx_timing.sdc
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Expand Up @@ -3,12 +3,6 @@
################################################################################
set_time_format -unit ns -decimal_places 3

################################################################################
#Read periphery constraints files
################################################################################
read_sdc LMS7002_timing.sdc


################################################################################
#Timing parameters
################################################################################
Expand Down Expand Up @@ -43,18 +37,18 @@ create_clock -period "1MHz" -name BRDG_SPI_SCLK [get_ports BRDG_SPI_SCLK]
create_generated_clock -name FPGA_SPI0_SCLK_reg \
-source [get_ports {FX3_PCLK}] \
-divide_by 6 \
[get_registers {nios_cpu:inst42|lms_ctr:u0|lms_ctr_spi_lms:spi_lms|SCLK_reg}]
[get_registers {*|lms_ctr_spi_lms:spi_lms|SCLK_reg}]

create_generated_clock -name FPGA_SPI0_SCLK_out \
-source [get_registers {nios_cpu:inst42|lms_ctr:u0|lms_ctr_spi_lms:spi_lms|SCLK_reg}] \
-source [get_registers {*|lms_ctr_spi_lms:spi_lms|SCLK_reg}] \
[get_ports FPGA_SPI0_SCLK]

set_false_path -to [get_ports FPGA_SPI0_SCLK]

create_generated_clock -name FPGA_SPI1_SCLK \
-source [get_ports FX3_PCLK] \
-divide_by 6 \
[get_registers nios_cpu:inst42|lms_ctr:u0|lms_ctr_spi_1_ADF:spi_1_adf|SCLK_reg]
[get_registers {*|lms_ctr_spi_1_ADF:spi_1_adf|SCLK_reg}]


################################################################################
Expand Down Expand Up @@ -96,34 +90,6 @@ set_output_delay -clock [get_clocks FPGA_SPI0_SCLK_out] -min -15 [get_ports {FPG
#set_multicycle_path -setup -from [get_clocks FX3_PCLK_VIRT ] -to [get_clocks FX3_PCLK] 2
#set_multicycle_path -hold -from [get_clocks FX3_PCLK_VIRT ] -to [get_clocks FX3_PCLK] 1

################################################################################
#Asyncronous clocks
################################################################################
# To clocks that are not related to each other
set_clock_groups -asynchronous -group {SI_CLK0} \
-group {SI_CLK1} \
-group {SI_CLK2} \
-group {SI_CLK3} \
-group {SI_CLK5} \
-group {SI_CLK6} \
-group {SI_CLK7} \
-group {LMK_CLK} \
-group {BRDG_SPI_SCLK} \
-group {LMS_MCLK1} \
-group {LMS_MCLK1_5MHZ} \
-group {TX_PLLCLK_C0 } \
-group {TX_PLLCLK_C1 LMS_FCLK1_PLL} \
-group {LMS_FCLK1_DRCT } \
-group {LMS_MCLK2} \
-group {LMS_MCLK2_5MHZ} \
-group {RX_PLLCLK_C0} \
-group {RX_PLLCLK_C1 } \
-group {LMS_FCLK2_PLL} \
-group {LMS_FCLK2_DRCT } \
-group {FX3_PCLK FPGA_SPI0_SCLK_reg FPGA_SPI0_SCLK_out} \
-group {inst27|DDR2_ctrl_top_inst|ddr2_inst|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1]} \
-group {inst46|ddr2_inst|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1]}


################################################################################
#NIOS constraints
Expand Down Expand Up @@ -185,21 +151,21 @@ set_false_path -to [get_ports FAN_CTRL*]
set_false_path -to [get_ports FPGA_SPI0_LMS_SS*]


set_multicycle_path -from [get_registers {rx_path_top:inst28|smpl_cnt:smpl_cnt_inst3|lpm_cnt_inst:lpm_cnt_inst_inst0|lpm_counter:LPM_COUNTER_component|cntr_f5l:auto_generated|counter_reg_bit[*]}] \
-to [get_registers {rx_path_top:inst28|smpl_cnt:smpl_cnt_inst3|lpm_cnt_inst:lpm_cnt_inst_inst0|lpm_counter:LPM_COUNTER_component|cntr_f5l:auto_generated|counter_reg_bit[*]}] \
set_multicycle_path -from [get_registers {*rx_path_top*|smpl_cnt:smpl_cnt_inst3|lpm_cnt_inst:lpm_cnt_inst_inst0|lpm_counter:LPM_COUNTER_component|cntr_f5l:auto_generated|counter_reg_bit[*]}] \
-to [get_registers {*rx_path_top*|smpl_cnt:smpl_cnt_inst3|lpm_cnt_inst:lpm_cnt_inst_inst0|lpm_counter:LPM_COUNTER_component|cntr_f5l:auto_generated|counter_reg_bit[*]}] \
-setup -end 2

set_multicycle_path -from [get_registers {rx_path_top:inst28|smpl_cnt:smpl_cnt_inst3|lpm_cnt_inst:lpm_cnt_inst_inst0|lpm_counter:LPM_COUNTER_component|cntr_f5l:auto_generated|counter_reg_bit[*]}] \
-to [get_registers {rx_path_top:inst28|smpl_cnt:smpl_cnt_inst3|lpm_cnt_inst:lpm_cnt_inst_inst0|lpm_counter:LPM_COUNTER_component|cntr_f5l:auto_generated|counter_reg_bit[*]}] \
set_multicycle_path -from [get_registers {*rx_path_top*|smpl_cnt:smpl_cnt_inst3|lpm_cnt_inst:lpm_cnt_inst_inst0|lpm_counter:LPM_COUNTER_component|cntr_f5l:auto_generated|counter_reg_bit[*]}] \
-to [get_registers {*rx_path_top*|smpl_cnt:smpl_cnt_inst3|lpm_cnt_inst:lpm_cnt_inst_inst0|lpm_counter:LPM_COUNTER_component|cntr_f5l:auto_generated|counter_reg_bit[*]}] \
-hold -end 1


set_multicycle_path -from [get_registers {rx_path_top:inst28|smpl_cnt:smpl_cnt_inst4|lpm_cnt_inst:lpm_cnt_inst_inst0|lpm_counter:LPM_COUNTER_component|cntr_f5l:auto_generated|counter_reg_bit[*]}] \
-to [get_registers {rx_path_top:inst28|smpl_cnt:smpl_cnt_inst4|lpm_cnt_inst:lpm_cnt_inst_inst0|lpm_counter:LPM_COUNTER_component|cntr_f5l:auto_generated|counter_reg_bit[*]}] \
set_multicycle_path -from [get_registers {*rx_path_top*|smpl_cnt:smpl_cnt_inst4|lpm_cnt_inst:lpm_cnt_inst_inst0|lpm_counter:LPM_COUNTER_component|cntr_f5l:auto_generated|counter_reg_bit[*]}] \
-to [get_registers {*rx_path_top*|smpl_cnt:smpl_cnt_inst4|lpm_cnt_inst:lpm_cnt_inst_inst0|lpm_counter:LPM_COUNTER_component|cntr_f5l:auto_generated|counter_reg_bit[*]}] \
-setup -end 2

set_multicycle_path -from [get_registers {rx_path_top:inst28|smpl_cnt:smpl_cnt_inst4|lpm_cnt_inst:lpm_cnt_inst_inst0|lpm_counter:LPM_COUNTER_component|cntr_f5l:auto_generated|counter_reg_bit[*]}] \
-to [get_registers {rx_path_top:inst28|smpl_cnt:smpl_cnt_inst4|lpm_cnt_inst:lpm_cnt_inst_inst0|lpm_counter:LPM_COUNTER_component|cntr_f5l:auto_generated|counter_reg_bit[*]}] \
set_multicycle_path -from [get_registers {*rx_path_top*|smpl_cnt:smpl_cnt_inst4|lpm_cnt_inst:lpm_cnt_inst_inst0|lpm_counter:LPM_COUNTER_component|cntr_f5l:auto_generated|counter_reg_bit[*]}] \
-to [get_registers {*rx_path_top*|smpl_cnt:smpl_cnt_inst4|lpm_cnt_inst:lpm_cnt_inst_inst0|lpm_counter:LPM_COUNTER_component|cntr_f5l:auto_generated|counter_reg_bit[*]}] \
-hold -end 1


Expand All @@ -211,14 +177,14 @@ set_false_path -to [get_ports LMS_FCLK1]
set_false_path -to [get_ports LMS_FCLK2]
set_false_path -to [get_ports FPGA_SPI1_SCLK]

set_false_path -to [get_registers tstcfg:inst39|dout_reg[*]]
set_false_path -to [get_registers *tstcfg*|dout_reg[*]]

set_false_path -from [get_registers {tstcfg:inst39|mem[3][5]}]
set_false_path -from [get_registers {fpgacfg:inst24|mem[13][2]}]
set_false_path -from [get_registers {ddr2_tester:inst46|ddr2_traffic_gen:traffic_gen_inst|ddr2_traffic_gen_mm_traffic_generator_0:mm_traffic_generator_0|driver_avl_use_be_avl_use_burstbegin:traffic_generator_0|pnf_per_bit_persist[*]}]
set_false_path -from [get_registers {wfm_player_top:inst27|DDR2_ctrl_top:DDR2_ctrl_top_inst|ddr2_traffic_gen:traffic_gen_inst|ddr2_traffic_gen_mm_traffic_generator_0:mm_traffic_generator_0|driver_avl_use_be_avl_use_burstbegin:traffic_generator_0|pnf_per_bit_persist[*]}]
set_false_path -from [get_registers {ddr2_tester:inst46|ddr2_traffic_gen:traffic_gen_inst|ddr2_traffic_gen_mm_traffic_generator_0:mm_traffic_generator_0|driver_avl_use_be_avl_use_burstbegin:traffic_generator_0|driver_fsm_avl_use_be_avl_use_burstbegin:real_driver.driver_fsm_inst|stage.TIMEOUT}]
set_false_path -from [get_registers {ddr2_tester:inst46|ddr2_traffic_gen:traffic_gen_inst|ddr2_traffic_gen_mm_traffic_generator_0:mm_traffic_generator_0|driver_avl_use_be_avl_use_burstbegin:traffic_generator_0|driver_fsm_avl_use_be_avl_use_burstbegin:real_driver.driver_fsm_inst|stage.TEST_COMPLETE}]
set_false_path -from [get_registers {*tstcfg*|mem[3][5]}]
set_false_path -from [get_registers {*fpgacfg*|mem[13][2]}]
set_false_path -from [get_registers {*ddr2_tester*|ddr2_traffic_gen:traffic_gen_inst|ddr2_traffic_gen_mm_traffic_generator_0:mm_traffic_generator_0|driver_avl_use_be_avl_use_burstbegin:traffic_generator_0|pnf_per_bit_persist[*]}]
set_false_path -from [get_registers {*wfm_player_top*|DDR2_ctrl_top:DDR2_ctrl_top_inst|ddr2_traffic_gen:traffic_gen_inst|ddr2_traffic_gen_mm_traffic_generator_0:mm_traffic_generator_0|driver_avl_use_be_avl_use_burstbegin:traffic_generator_0|pnf_per_bit_persist[*]}]
set_false_path -from [get_registers {*ddr2_tester*|ddr2_traffic_gen:traffic_gen_inst|ddr2_traffic_gen_mm_traffic_generator_0:mm_traffic_generator_0|driver_avl_use_be_avl_use_burstbegin:traffic_generator_0|driver_fsm_avl_use_be_avl_use_burstbegin:real_driver.driver_fsm_inst|stage.TIMEOUT}]
set_false_path -from [get_registers {*ddr2_tester*|ddr2_traffic_gen:traffic_gen_inst|ddr2_traffic_gen_mm_traffic_generator_0:mm_traffic_generator_0|driver_avl_use_be_avl_use_burstbegin:traffic_generator_0|driver_fsm_avl_use_be_avl_use_burstbegin:real_driver.driver_fsm_inst|stage.TEST_COMPLETE}]
set_false_path -from [get_registers *sync_reg0\[*\]]


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