GitHub - nadabadawi/CMOS_Circuits_Characterization: 2 different variations of each cell was tested: NAND, INV, and NOR. Each cell was connected to a voltage source and a load capacitor. The experiment involved changing the input transition and the load cap. to measure the time delay. A python script was written to automate the process of writing a spice netlist for each cell to change the variables.

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2 different variations of each cell was tested: NAND, INV, and NOR. Each cell was connected to a voltage source and a load capacitor. The experiment involved changing the input transition and the load cap. to measure the time delay. A python script was written to automate the process of writing a spice netlist for each cell to change the variables.