Single-Cycle MIPS

A System Verilog processor design of a single cycle MIPS architecture.
Available for running at: https://www.edaplayground.com/x/5Eje

Architecture and micro-architecture data:

• Supports 32 bit standard MIPS instructions
• Has 32 data registers of 32 bits
• Has data memory of 256 bytes

R-type instructions (add, sub, set less than, jump register) structure:

Op	rs	rt	rd	shamt	funct
6 bits	5 bits	5 bits	5 bits	5 bits	6 bits

I-type instructions (load word, store word, branch not equal, branch equal, add immediate, load upper immediate) structure:

Op	rs	rt	Immediate value / address offset (in 2's complement)
6 bits	5 bits	5 bits	16 bits

Common instructions and resulting signals of ALUOp and ALU control:

Instruction	Opcode	Funct	ALUOp	ALU ctrl	Function
lw	35	--	00	010	ADD
sw	43	--	00	010	ADD
beq	4	--	01	110	SUB
add	0	32	10	010	ADD
sub	0	34	10	110	SUB
and	0	36	10	000	AND
or	0	37	10	001	OR
slt	0	42	10	111	SLT

Name		Name	Last commit message	Last commit date
Latest commit History 9 Commits
MIPS_connectivity(main).sv		MIPS_connectivity(main).sv
MIPS_controller.txt		MIPS_controller.txt
MIPS_datapath_components.txt		MIPS_datapath_components.txt
MIPS_intructions.txt		MIPS_intructions.txt
MIPS_testbench.txt		MIPS_testbench.txt
README.md		README.md
SIngle Cycle MIPS Diagram.png		SIngle Cycle MIPS Diagram.png

Instruction	Opcode	Funct	ALUOp	ALU ctrl	Function
lw	35	--	00	010	ADD
sw	43	--	00	010	ADD
beq	4	--	01	110	SUB
add	0	32	10	010	ADD
sub	0	34	10	110	SUB
and	0	36	10	000	AND
or	0	37	10	001	OR
slt	0	42	10	111	SLT

Instruction	Opcode	Funct	ALUOp	ALU ctrl	Function
lw	35	--	00	010	ADD
sw	43	--	00	010	ADD
beq	4	--	01	110	SUB
add	0	32	10	010	ADD
sub	0	34	10	110	SUB
and	0	36	10	000	AND
or	0	37	10	001	OR
slt	0	42	10	111	SLT

Instruction	Opcode	Funct	ALUOp	ALU ctrl	Function
lw	35	--	00	010	ADD
sw	43	--	00	010	ADD
beq	4	--	01	110	SUB
add	0	32	10	010	ADD
sub	0	34	10	110	SUB
and	0	36	10	000	AND
or	0	37	10	001	OR
slt	0	42	10	111	SLT