Skip to content
View nanamake's full-sized avatar

Block or report nanamake

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. r22sdf r22sdf Public

    Pipeline FFT Implementation in Verilog HDL

    Verilog 71 18

  2. vcd2json vcd2json Public

    Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.

    Python 33 13

  3. avr_cpu avr_cpu Public

    AVR CPU Core Implementation in Verilog HDL.

    Verilog 5 1

  4. pseudo_hdl pseudo_hdl Public

    Pseudo HDL and its simulator written in Python.

    Python 1