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Merge branch 'develop' of github.com:newaetech/chipwhisperer into dev…
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…elop
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@alex-dewar
alex-dewar committed Sep 20, 2021
2 parents b5ae140 + a3cd447 commit a903ab3
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Showing 2 changed files with 50 additions and 43 deletions.
23 changes: 11 additions & 12 deletions software/chipwhisperer/capture/scopes/_OpenADCInterface.py
View file
Expand Up @@ -2185,8 +2185,9 @@ def setStreamSegmentSize(self, size):
self._stream_segment_size = size


def setFastSMC(self, fast):
self.serial.set_smc_speed(fast)
def setFastSMC(self, active):
self.setFastFIFORead(active)
self.serial.set_smc_speed(active)

def setBitsPerSample(self, bits):
self._bits_per_sample = bits
Expand Down Expand Up @@ -2573,9 +2574,8 @@ def startCaptureThread(self):
if self._stream_mode:
# Stream mode adds 500mS of extra timeout on USB traffic itself...
scope_logger.debug("Stream on!")
if self._is_husky:
self.setFastFIFORead(1)
self.serial.set_smc_speed(1)
if self._is_husky and self._fast_fifo_read_enable:
self.setFastSMC(1)
self.serial.initStreamModeCapture(self._stream_len, self._sbuf, timeout_ms=int(self._timeout * 1000) + 500, \
is_husky=self._is_husky, segment_size=self._stream_segment_size)

Expand Down Expand Up @@ -2603,10 +2603,9 @@ def capture(self, offset=None, adc_freq=29.53E6, samples=24400):
self.serial.streamModeCaptureStream.stop = True
break

if self._is_husky:
if self._is_husky and self._fast_fifo_read_enable:
scope_logger.debug("DISABLING fast fifo read")
self.setFastFIFORead(0)
self.serial.set_smc_speed(0)
self.setFastSMC(0)

self._stream_rx_bytes, stream_timeout = self.serial.cmdReadStream(self._is_husky)
timeout |= stream_timeout
Expand Down Expand Up @@ -2831,12 +2830,12 @@ def readHuskyData(self, NumberPoints=None):
else:
if self._fast_fifo_read_enable:
# switch FPGA and SAM3U into fast read timing mode
self.setFastFIFORead(1)
self.serial.set_smc_speed(1)
self.setFastSMC(1)
data = self.sendMessage(CODE_READ, ADDR_ADCDATA, None, False, bytesToRead)
# switch FPGA and SAM3U back to regular read timing mode
self.setFastFIFORead(0)
self.serial.set_smc_speed(0)
if self._fast_fifo_read_enable:
scope_logger.debug("DISABLING fast fifo read")
self.setFastSMC(0)

scope_logger.debug("XXX read %d bytes; NumberPoints=%d, bytesToRead=%d" % (len(data), NumberPoints, bytesToRead))
if data is not None:
Expand Down
70 changes: 39 additions & 31 deletions tests/test_husky.py
View file
Expand Up @@ -132,37 +132,41 @@ def find0to1trans(data):


testData = [
# samples presamples testmode clock adcmul bit stream segs segcycs desc
(10, 0, 'internal', 20e6, 1, 8, False, 1, 0, 'quick'),
(131070, 0, 'internal', 20e6, 1, 8, False, 1, 0, 'maxsamples8'),
(131070, 0, 'internal', 20e6, 1, 12, False, 1, 0, 'maxsamples12'),
(300, 0, 'internal', 20e6, 1, 8, False, 10, 1000, 'evensegments8'),
(50, 0, 'internal', 20e6, 1, 8, False, 100, 100, 'oddsegments8'),
(300, 0, 'internal', 20e6, 1, 12, False, 10, 1000, 'evensegments12'),
(50, 0, 'internal', 20e6, 1, 12, False, 100, 100, 'oddsegments12'),
(300, 30, 'internal', 20e6, 1, 12, False, 20, 500, 'presamplesegments'),
(131070, 0, 'internal', 10e6, 1, 12, False, 1, 0, 'slow'),
(131070, 0, 'internal', 80e6, 1, 12, False, 1, 0, 'fast'),
(131070, 0, 'internal', 180e6, 1, 12, False, 1, 0, 'fastest'),
(131070, 0, 'internal', 5e6, 4, 12, False, 1, 0, '4xslow'),
(131070, 0, 'internal', 45e6, 4, 12, False, 1, 0, '4xfast'),
(131070, 0, 'ADC', 20e6, 1, 12, False, 1, 0, 'ADCslow'),
(131070, 0, 'ADC', 180e6, 1, 12, False, 1, 0, 'ADCfast'),
(131070, 0, 'ADC', 45e6, 4, 12, False, 1, 0, 'ADC4xfast'),
# samples presamples testmode clock fastreads adcmul bit stream segs segcycs desc
(10, 0, 'internal', 20e6, True, 1, 8, False, 1, 0, 'quick'),
(131070, 0, 'internal', 20e6, True, 1, 8, False, 1, 0, 'maxsamples8'),
(131070, 0, 'internal', 20e6, True, 1, 12, False, 1, 0, 'maxsamples12'),
(300, 0, 'internal', 20e6, True, 1, 8, False, 10, 1000, 'evensegments8'),
(50, 0, 'internal', 20e6, True, 1, 8, False, 100, 100, 'oddsegments8'),
(300, 0, 'internal', 20e6, True, 1, 12, False, 10, 1000, 'evensegments12'),
(50, 0, 'internal', 20e6, True, 1, 12, False, 100, 100, 'oddsegments12'),
(300, 30, 'internal', 20e6, True, 1, 12, False, 20, 500, 'presamplesegments'),
(131070, 0, 'internal', 10e6, True, 1, 12, False, 1, 0, 'slow'),
(131070, 0, 'internal', 80e6, True, 1, 12, False, 1, 0, 'fast'),
(131070, 0, 'internal', 180e6, True, 1, 12, False, 1, 0, 'fastest'),
(131070, 0, 'internal', 5e6, True, 4, 12, False, 1, 0, '4xslow'),
(131070, 0, 'internal', 45e6, True, 4, 12, False, 1, 0, '4xfast'),
(131070, 0, 'ADC', 20e6, True, 1, 12, False, 1, 0, 'ADCslow'),
(131070, 0, 'ADC', 180e6, True, 1, 12, False, 1, 0, 'ADCfast'),
(131070, 0, 'ADC', 45e6, True, 4, 12, False, 1, 0, 'ADC4xfast'),
(500, 0, 'internal', 20e6, False, 1, 12, False, 1, 0, 'slowreads'),
(131070, 0, 'internal', 20e6, False, 1, 12, False, 1, 0, 'maxslowreads'),
]


testTargetData = [
# samples presamples testmode clock adcmul bit stream threshold check segs segcycs desc
(200, 0, 'internal', 20e6, 1, 8, False, 65536, True, 1, 0, 'quick'),
(131070, 0, 'internal', 15e6, 1, 12, False, 65536, True, 1, 0, 'maxsamples12'),
(200000, 0, 'internal', 20e6, 1, 8, True , 65536, True, 1, 0, 'quickstream8'),
(2000000, 0, 'internal', 16e6, 1, 12, True , 65536, True, 1, 0, 'longstream12'),
(6000000, 0, 'internal', 16e6, 1, 12, True , 65536, False, 1, 0, 'vlongstream12'),
(500000, 0, 'internal', 20e6, 1, 12, True , 16384, True, 1, 0, 'over'),
(3000000, 0, 'internal', 24e6, 1, 12, True , 65536, False, 1, 0, 'overflow'),
(200000, 0, 'internal', 15e6, 1, 12, True , 65536, True, 1, 0, 'postfail'),
(2000, 0, 'internal', 10e6, 1, 8, False, 65536, True, 1, 0, 'back2nostream'),
# samples presamples testmode clock fastreads adcmul bit stream threshold check segs segcycs desc
(200, 0, 'internal', 20e6, True, 1, 8, False, 65536, True, 1, 0, 'quick'),
(131070, 0, 'internal', 15e6, True, 1, 12, False, 65536, True, 1, 0, 'maxsamples12'),
(200000, 0, 'internal', 20e6, True, 1, 8, True , 65536, True, 1, 0, 'quickstream8'),
(2000000, 0, 'internal', 16e6, True, 1, 12, True , 65536, True, 1, 0, 'longstream12'),
(6000000, 0, 'internal', 16e6, True, 1, 12, True , 65536, False, 1, 0, 'vlongstream12'),
(500000, 0, 'internal', 20e6, True, 1, 12, True , 16384, True, 1, 0, 'over'),
(3000000, 0, 'internal', 24e6, True, 1, 12, True , 65536, False, 1, 0, 'overflow'),
(200000, 0, 'internal', 15e6, True, 1, 12, True , 65536, True, 1, 0, 'postfail'),
(2000, 0, 'internal', 10e6, True, 1, 8, False, 65536, True, 1, 0, 'back2nostream'),
(500000, 0, 'internal', 12e6, False, 1, 12, True , 65536, True, 1, 0, 'slowreads1'),
(2000000, 0, 'internal', 10e6, False, 1, 12, True , 65536, True, 1, 0, 'slowreads2'),
]

testGlitchOffsetData = [
Expand Down Expand Up @@ -221,8 +225,8 @@ def test_fw_version():
assert scope.sam_build_date == '17:03:04 Aug 24 2021'


@pytest.mark.parametrize("samples, presamples, testmode, clock, adcmul, bits, stream, segments, segment_cycles, desc", testData)
def test_internal_ramp(samples, presamples, testmode, clock, adcmul, bits, stream, segments, segment_cycles, desc):
@pytest.mark.parametrize("samples, presamples, testmode, clock, fastreads, adcmul, bits, stream, segments, segment_cycles, desc", testData)
def test_internal_ramp(samples, presamples, testmode, clock, fastreads, adcmul, bits, stream, segments, segment_cycles, desc):
scope.clock.clkgen_freq = clock
scope.clock.adc_mul = adcmul
time.sleep(0.1)
Expand All @@ -238,6 +242,7 @@ def test_internal_ramp(samples, presamples, testmode, clock, adcmul, bits, strea
else:
raise ValueError

scope.sc._fast_fifo_read_enable = fastreads
scope.adc.stream_mode = stream
scope.adc.samples = samples
scope.adc.presamples = presamples
Expand All @@ -253,6 +258,7 @@ def test_internal_ramp(samples, presamples, testmode, clock, adcmul, bits, strea
raw = scope.get_last_trace(True)
assert check_ramp(raw, testmode, samples, segment_cycles) == 0
assert scope.adc.errors == 'no errors'
scope.sc._fast_fifo_read_enable = True # return to default


def setup_glitch(offset, width, oversamp):
Expand Down Expand Up @@ -447,9 +453,9 @@ def test_glitch_output_doubles(reps, vco, glitches, oversamp, stepsize, desc):



@pytest.mark.parametrize("samples, presamples, testmode, clock, adcmul, bits, stream, threshold, check, segments, segment_cycles, desc", testTargetData)
@pytest.mark.parametrize("samples, presamples, testmode, clock, fastreads, adcmul, bits, stream, threshold, check, segments, segment_cycles, desc", testTargetData)
@pytest.mark.skipif(not target_attached, reason='No target detected')
def test_target_internal_ramp (samples, presamples, testmode, clock, adcmul, bits, stream, threshold, check, segments, segment_cycles, desc):
def test_target_internal_ramp (samples, presamples, testmode, clock, fastreads, adcmul, bits, stream, threshold, check, segments, segment_cycles, desc):
scope.clock.clkgen_freq = clock
scope.clock.adc_mul = adcmul
time.sleep(0.1)
Expand Down Expand Up @@ -482,6 +488,7 @@ def test_target_internal_ramp (samples, presamples, testmode, clock, adcmul, bit
scope.io.tio2 = "serial_tx"
scope.io.hs2 = "clkgen"

scope.sc._fast_fifo_read_enable = fastreads
scope.adc.samples = samples
scope.adc.presamples = presamples
scope.adc.segments = segments
Expand All @@ -500,6 +507,7 @@ def test_target_internal_ramp (samples, presamples, testmode, clock, adcmul, bit
else:
assert scope.adc.errors == 'no errors'
if check: assert check_ramp(raw, testmode, samples, segment_cycles) == 0
scope.sc._fast_fifo_read_enable = True # return to default


def test_xadc():
Expand Down

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