GitHub - ngaar/LC3_verilog: Verilog implementation of LC3 architecture

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Verilog implementation of LC3 architecture

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Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
Makefile		Makefile
README		README
clock.v		clock.v
counter.v		counter.v
cpu		cpu
cpu.v		cpu.v
cpu.v.save		cpu.v.save
cpu.vcd		cpu.vcd
mem.hex		mem.hex
mem.v		mem.v
mem2.hex		mem2.hex
mem4.hex		mem4.hex
mem5.hex		mem5.hex
mem6.hex		mem6.hex
mem7.hex		mem7.hex
mem8.hex		mem8.hex
mem9.hex		mem9.hex
mema.hex		mema.hex
memb.hex		memb.hex
memc.hex		memc.hex
memd.hex		memd.hex
meme.hex		meme.hex
memf.hex		memf.hex
memg.hex		memg.hex
memh.hex		memh.hex
regs.v		regs.v
test.cycles		test.cycles
test.ok		test.ok
test.out		test.out
test.raw		test.raw
test2.ok		test2.ok
test4.ok		test4.ok
test5.ok		test5.ok
test6.ok		test6.ok
test7.ok		test7.ok
test8.ok		test8.ok
test9.ok		test9.ok
testa.ok		testa.ok
testb.ok		testb.ok
testc.ok		testc.ok
testd.ok		testd.ok
teste.ok		teste.ok
testf.ok		testf.ok
testg.ok		testg.ok
testh.ok		testh.ok

Repository files navigation

Due date: 12/4/2015 @ 11:59pm

Assignment:
~~~~~~~~~~~

- Implement your proposed project
- Finish REPORT.txt

  The instructions we implemented:
        OPCODE     
      15 14 13 12|11 10 9 8 7 6 5 4 3 2 1 0
  ADD+ 0  0  0 1 |   DR  | SR1 |0|0 0|SR2  
  ADD+ 0  0  0 1 |   DR  | SR1 |1|immed val
  AND+ 0  1  0 1 |   DR  | SR1 |0|0 0|SR2 
  AND+ 0  1  0 1 |   DR  | SR1 |1|immed val
  JMP  1  1  0 0 | 0 0  0|Base |0 0 0 0 0 0
  LD+  0  0  1 0 |   DR  | PCoffset9 bit number
  LDI+ 0  1  1 0 |   DR  | PCoffset9 bit number
  LDR+ 0  1  1 0 |   DR  |Base | offset6 bit 
  LEA  1  1  1 0 |   DR  |  PCoffset9 bit
  NOT+ 1  0  0 1 |   DR  | SR  |1 1 1 1 1 1
  ST   0  0  1 1 |   SR  | PCoffset9 bit number
  STI  1  0  1 1 |   SR  | PCoffset9 bit number
  STR  0  1  1 1 |   SR  | BASE |  offset6 bit
  MOV  1  1  0 1 |   DR  | 9 bit bit imme number

 ADD: dr = sr1 + sr2
 ADD: dr = sr1 + immed_val
 AND: dr = sr1 && sr2
 AND: dr = sr1 && immed_val
 JMP: PC = baseR
 LD:  dr = mem[pc + offset]
 LDI: dr = mem[mem[baser + offset]]
 LDR: dr = mem[baser + offset]
 LEA: dr = pc + offset
 NOT: dr = ~sr
 ST : mem[pc + offset] = sr
 STI: mem[mem[pc+ offset]] = sr
 STR: mem[baser + offset] = sr
 MOV: dr = 9 bit offset  

 
 DR: Destination register
 SR1: Source Register
 SR2: Source Register
 PCoffset9 : indicates the 9 bit number + PC
 PCoffset6 : indicated the 6 bit number + PC
 BASE: register value (base register) 

- Running instructions (concrete and concise):

    For example:

        - make clean
        - make clean test
        - make clean test should run our whole test suite