forked from steveicarus/iverilog
-
Notifications
You must be signed in to change notification settings - Fork 1
/
elaborate.cc
2442 lines (2028 loc) · 69.1 KB
/
elaborate.cc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT) && !defined(macintosh)
#ident "$Id: elaborate.cc,v 1.165 2000/04/28 23:12:12 steve Exp $"
#endif
/*
* Elaboration takes as input a complete parse tree and the name of a
* root module, and generates as output the elaborated design. This
* elaborated design is presented as a Module, which does not
* reference any other modules. It is entirely self contained.
*/
# include <typeinfo>
# include <strstream>
# include "pform.h"
# include "PEvent.h"
# include "netlist.h"
# include "netmisc.h"
# include "util.h"
// Urff, I don't like this global variable. I *will* figure out a
// way to get rid of it. But, for now the PGModule::elaborate method
// needs it to find the module definition.
static const map<string,Module*>* modlist = 0;
static const map<string,PUdp*>* udplist = 0;
/*
* Elaborate a source wire. The "wire" is the declaration of wires,
* registers, ports and memories. The parser has already merged the
* multiple properties of a wire (i.e. "input wire") so come the
* elaboration this creates an object in the design that represent the
* defined item.
*/
void PWire::elaborate(Design*des, NetScope*scope) const
{
/* The parser may produce hierarchical names for wires. I here
follow the scopes down to the base where I actually want to
elaborate the NetNet object. */
string basename = name_;
for (;;) {
string p = parse_first_name(basename);
if (basename == "") {
basename = p;
break;
}
scope = scope->child(p);
assert(scope);
}
const string path = scope->name();
NetNet::Type wtype = type_;
if (wtype == NetNet::IMPLICIT)
wtype = NetNet::WIRE;
if (wtype == NetNet::IMPLICIT_REG)
wtype = NetNet::REG;
unsigned wid = 1;
long lsb = 0, msb = 0;
if (msb_.count()) {
svector<long>mnum (msb_.count());
svector<long>lnum (msb_.count());
/* There may be multiple declarations of ranges, because
the symbol may have its range declared in i.e. input
and reg declarations. Calculate *all* the numbers
here. I will resolve the values later. */
for (unsigned idx = 0 ; idx < msb_.count() ; idx += 1) {
verinum*mval = msb_[idx]->eval_const(des,path);
if (mval == 0) {
cerr << msb_[idx]->get_line() << ": error: "
"Unable to evaluate constant expression ``" <<
*msb_[idx] << "''." << endl;
des->errors += 1;
return;
}
verinum*lval = lsb_[idx]->eval_const(des, path);
if (mval == 0) {
cerr << lsb_[idx]->get_line() << ": error: "
"Unable to evaluate constant expression ``" <<
*lsb_[idx] << "''." << endl;
des->errors += 1;
return;
}
mnum[idx] = mval->as_long();
lnum[idx] = lval->as_long();
delete mval;
delete lval;
}
/* Make sure all the values for msb and lsb match by
value. If not, report an error. */
for (unsigned idx = 1 ; idx < msb_.count() ; idx += 1) {
if ((mnum[idx] != mnum[0]) || (lnum[idx] != lnum[0])) {
cerr << get_line() << ": error: Inconsistent width, "
"[" << mnum[idx] << ":" << lnum[idx] << "]"
" vs. [" << mnum[0] << ":" << lnum[0] << "]"
" for signal ``" << basename << "''" << endl;
des->errors += 1;
return;
}
}
lsb = lnum[0];
msb = mnum[0];
if (mnum[0] > lnum[0])
wid = mnum[0] - lnum[0] + 1;
else
wid = lnum[0] - mnum[0] + 1;
}
if (lidx_ || ridx_) {
assert(lidx_ && ridx_);
// If the register has indices, then this is a
// memory. Create the memory object.
verinum*lval = lidx_->eval_const(des, path);
assert(lval);
verinum*rval = ridx_->eval_const(des, path);
assert(rval);
long lnum = lval->as_long();
long rnum = rval->as_long();
delete lval;
delete rval;
NetMemory*sig = new NetMemory(path+"."+basename, wid, lnum, rnum);
sig->set_attributes(attributes);
des->add_memory(sig);
} else {
NetNet*sig = new NetNet(scope, path + "." +basename, wtype, msb, lsb);
sig->set_line(*this);
sig->port_type(port_type_);
sig->set_attributes(attributes);
verinum::V iv = verinum::Vz;
if (wtype == NetNet::REG)
iv = verinum::Vx;
for (unsigned idx = 0 ; idx < wid ; idx += 1)
sig->set_ival(idx, iv);
des->add_signal(sig);
}
}
void PGate::elaborate(Design*des, const string&path) const
{
cerr << "internal error: what kind of gate? " <<
typeid(*this).name() << endl;
}
/*
* Elaborate the continuous assign. (This is *not* the procedural
* assign.) Elaborate the lvalue and rvalue, and do the assignment.
*/
void PGAssign::elaborate(Design*des, const string&path) const
{
unsigned long rise_time, fall_time, decay_time;
eval_delays(des, path, rise_time, fall_time, decay_time);
assert(pin(0));
assert(pin(1));
/* Elaborate the l-value. */
NetNet*lval = pin(0)->elaborate_lnet(des, path);
if (lval == 0) {
des->errors += 1;
return;
}
/* Elaborate the r-value. Account for the initial decays,
which are going to be attached to the last gate before the
generated NetNet. */
NetNet*rval = pin(1)->elaborate_net(des, path,
lval->pin_count(),
rise_time, fall_time, decay_time);
if (rval == 0) {
cerr << get_line() << ": error: Unable to elaborate r-value: "
<< *pin(1) << endl;
des->errors += 1;
return;
}
assert(lval && rval);
if (lval->pin_count() > rval->pin_count()) {
cerr << get_line() << ": sorry: lval width (" <<
lval->pin_count() << ") > rval width (" <<
rval->pin_count() << ")." << endl;
delete lval;
delete rval;
des->errors += 1;
return;
}
for (unsigned idx = 0 ; idx < lval->pin_count() ; idx += 1)
connect(lval->pin(idx), rval->pin(idx));
if (lval->local_flag())
delete lval;
}
/*
* Elaborate a Builtin gate. These normally get translated into
* NetLogic nodes that reflect the particular logic function.
*/
void PGBuiltin::elaborate(Design*des, const string&path) const
{
unsigned count = 1;
unsigned low = 0, high = 0;
string name = get_name();
if (name == "")
name = des->local_symbol(path);
else
name = path+"."+name;
/* If the verilog source has a range specification for the
gates, then I am expected to make more then one
gate. Figure out how many are desired. */
if (msb_) {
verinum*msb = msb_->eval_const(des, path);
verinum*lsb = lsb_->eval_const(des, path);
if (msb == 0) {
cerr << get_line() << ": error: Unable to evaluate "
"expression " << *msb_ << endl;
des->errors += 1;
return;
}
if (lsb == 0) {
cerr << get_line() << ": error: Unable to evaluate "
"expression " << *lsb_ << endl;
des->errors += 1;
return;
}
if (msb->as_long() > lsb->as_long())
count = msb->as_long() - lsb->as_long() + 1;
else
count = lsb->as_long() - msb->as_long() + 1;
low = lsb->as_long();
high = msb->as_long();
}
/* Allocate all the getlist nodes for the gates. */
NetLogic**cur = new NetLogic*[count];
assert(cur);
/* Calculate the gate delays from the delay expressions
given in the source. For logic gates, the decay time
is meaningless because it can never go to high
impedence. However, the bufif devices can generate
'bz output, so we will pretend that anything can.
If only one delay value expression is given (i.e. #5
nand(foo,...)) then rise, fall and decay times are
all the same value. If two values are given, rise and
fall times are use, and the decay time is the minimum
of the rise and fall times. Finally, if all three
values are given, they are taken as specified. */
unsigned long rise_time, fall_time, decay_time;
eval_delays(des, path, rise_time, fall_time, decay_time);
/* Now make as many gates as the bit count dictates. Give each
a unique name, and set the delay times. */
for (unsigned idx = 0 ; idx < count ; idx += 1) {
strstream tmp;
unsigned index;
if (low < high)
index = low + idx;
else
index = low - idx;
tmp << name << "<" << index << ">" << ends;
const string inm = tmp.str();
switch (type()) {
case AND:
cur[idx] = new NetLogic(inm, pin_count(), NetLogic::AND);
break;
case BUF:
cur[idx] = new NetLogic(inm, pin_count(), NetLogic::BUF);
break;
case BUFIF0:
cur[idx] = new NetLogic(inm, pin_count(), NetLogic::BUFIF0);
break;
case BUFIF1:
cur[idx] = new NetLogic(inm, pin_count(), NetLogic::BUFIF1);
break;
case NAND:
cur[idx] = new NetLogic(inm, pin_count(), NetLogic::NAND);
break;
case NOR:
cur[idx] = new NetLogic(inm, pin_count(), NetLogic::NOR);
break;
case NOT:
cur[idx] = new NetLogic(inm, pin_count(), NetLogic::NOT);
break;
case OR:
cur[idx] = new NetLogic(inm, pin_count(), NetLogic::OR);
break;
case XNOR:
cur[idx] = new NetLogic(inm, pin_count(), NetLogic::XNOR);
break;
case XOR:
cur[idx] = new NetLogic(inm, pin_count(), NetLogic::XOR);
break;
default:
cerr << get_line() << ": internal error: unhandled "
"gate type." << endl;
des->errors += 1;
return;
}
cur[idx]->set_attributes(attributes);
cur[idx]->rise_time(rise_time);
cur[idx]->fall_time(fall_time);
cur[idx]->decay_time(decay_time);
des->add_node(cur[idx]);
}
/* The gates have all been allocated, this loop runs through
the parameters and attaches the ports of the objects. */
for (unsigned idx = 0 ; idx < pin_count() ; idx += 1) {
const PExpr*ex = pin(idx);
NetNet*sig = ex->elaborate_net(des, path, 0, 0, 0, 0);
if (sig == 0)
continue;
assert(sig);
if (sig->pin_count() == 1)
for (unsigned gdx = 0 ; gdx < count ; gdx += 1)
connect(cur[gdx]->pin(idx), sig->pin(0));
else if (sig->pin_count() == count)
for (unsigned gdx = 0 ; gdx < count ; gdx += 1)
connect(cur[gdx]->pin(idx), sig->pin(gdx));
else {
cerr << get_line() << ": error: Gate count of " <<
count << " does not match net width of " <<
sig->pin_count() << " at pin " << idx << "."
<< endl;
des->errors += 1;
}
if (NetTmp*tmp = dynamic_cast<NetTmp*>(sig))
delete tmp;
}
}
/*
* Instantiate a module by recursively elaborating it. Set the path of
* the recursive elaboration so that signal names get properly
* set. Connect the ports of the instantiated module to the signals of
* the parameters. This is done with BUFZ gates so that they look just
* like continuous assignment connections.
*/
void PGModule::elaborate_mod_(Design*des, Module*rmod, const string&path) const
{
// Missing module instance names have already been rejected.
assert(get_name() != "");
if (msb_) {
cerr << get_line() << ": sorry: Module instantiation arrays "
"are not yet supported." << endl;
des->errors += 1;
return;
}
NetScope*scope = des->find_scope(path);
assert(scope);
// I know a priori that the elaborate_scope created the scope
// already, so just look it up as a child of the current scope.
NetScope*my_scope = scope->child(get_name());
assert(my_scope);
const string my_name = my_scope -> name();
const svector<PExpr*>*pins;
// Detect binding by name. If I am binding by name, then make
// up a pins array that reflects the positions of the named
// ports. If this is simply positional binding in the first
// place, then get the binding from the base class.
if (pins_) {
unsigned nexp = rmod->port_count();
svector<PExpr*>*exp = new svector<PExpr*>(nexp);
// Scan the bindings, matching them with port names.
for (unsigned idx = 0 ; idx < npins_ ; idx += 1) {
// Given a binding, look at the module port names
// for the position that matches the binding name.
unsigned pidx = rmod->find_port(pins_[idx].name);
// If the port name doesn't exist, the find_port
// method will return the port count. Detect that
// as an error.
if (pidx == nexp) {
cerr << get_line() << ": error: port ``" <<
pins_[idx].name << "'' is not a port of "
<< get_name() << "." << endl;
des->errors += 1;
continue;
}
// If I already bound something to this port, then
// the (*exp) array will already have a pointer
// value where I want to place this expression.
if ((*exp)[pidx]) {
cerr << get_line() << ": error: port ``" <<
pins_[idx].name << "'' already bound." <<
endl;
des->errors += 1;
continue;
}
// OK, do the binding by placing the expression in
// the right place.
(*exp)[pidx] = pins_[idx].parm;
}
pins = exp;
} else {
if (pin_count() != rmod->port_count()) {
cerr << get_line() << ": error: Wrong number "
"of parameters. Expecting " << rmod->port_count() <<
", got " << pin_count() << "."
<< endl;
des->errors += 1;
return;
}
// No named bindings, just use the positional list I
// already have.
assert(pin_count() == rmod->port_count());
pins = get_pins();
}
// Elaborate this instance of the module. The recursive
// elaboration causes the module to generate a netlist with
// the ports represented by NetNet objects. I will find them
// later.
rmod->elaborate(des, my_scope);
// Now connect the ports of the newly elaborated designs to
// the expressions that are the instantiation parameters. Scan
// the pins, elaborate the expressions attached to them, and
// bind them to the port of the elaborated module.
for (unsigned idx = 0 ; idx < pins->count() ; idx += 1) {
// Skip unconnected module ports.
if ((*pins)[idx] == 0)
continue;
// Inside the module, the port is one or more signals,
// that were already elaborated. List all those signals,
// and I will connect them up later.
svector<PWire*> mport = rmod->get_port(idx);
svector<NetNet*>prts (mport.count());
unsigned prts_pin_count = 0;
for (unsigned ldx = 0 ; ldx < mport.count() ; ldx += 1) {
PWire*pport = mport[ldx];
prts[ldx] = des->find_signal(my_name, pport->name());
assert(prts[ldx]);
prts_pin_count += prts[ldx]->pin_count();
}
NetNet*sig = (*pins)[idx]->elaborate_net(des, path,
prts_pin_count,
0, 0, 0);
if (sig == 0) {
cerr << "internal error: Expression too complicated "
"for elaboration." << endl;
continue;
}
assert(sig);
// Check that the parts have matching pin counts. If
// not, they are different widths.
if (prts_pin_count != sig->pin_count()) {
cerr << get_line() << ": error: Port " << idx << " of "
<< type_ << " expects " << prts_pin_count <<
" pins, got " << sig->pin_count() << " from "
<< sig->name() << endl;
des->errors += 1;
continue;
}
// Connect the sig expression that is the context of the
// module instance to the ports of the elaborated
// module.
assert(prts_pin_count == sig->pin_count());
for (unsigned ldx = 0 ; ldx < prts.count() ; ldx += 1) {
for (unsigned p = 0 ; p < prts[ldx]->pin_count() ; p += 1) {
prts_pin_count -= 1;
connect(sig->pin(prts_pin_count),
prts[ldx]->pin(prts[ldx]->pin_count()-p-1));
}
}
if (NetTmp*tmp = dynamic_cast<NetTmp*>(sig))
delete tmp;
}
}
void PGModule::elaborate_cudp_(Design*des, PUdp*udp, const string&path) const
{
const string my_name = path+"."+get_name();
NetUDP_COMB*net = new NetUDP_COMB(my_name, udp->ports.count());
net->set_attributes(udp->attributes);
/* Run through the pins, making netlists for the pin
expressions and connecting them to the pin in question. All
of this is independent of the nature of the UDP. */
for (unsigned idx = 0 ; idx < net->pin_count() ; idx += 1) {
if (pin(idx) == 0)
continue;
NetNet*sig = pin(idx)->elaborate_net(des, path, 1, 0, 0, 0);
if (sig == 0) {
cerr << "internal error: Expression too complicated "
"for elaboration:" << *pin(idx) << endl;
continue;
}
connect(sig->pin(0), net->pin(idx));
// Delete excess holding signal.
if (NetTmp*tmp = dynamic_cast<NetTmp*>(sig))
delete tmp;
}
/* Build up the truth table for the netlist from the input
strings. */
for (unsigned idx = 0 ; idx < udp->tinput.count() ; idx += 1) {
string input = udp->tinput[idx];
net->set_table(input, udp->toutput[idx]);
}
net->cleanup_table();
// All done. Add the object to the design.
des->add_node(net);
}
/*
* From a UDP definition in the source, make a NetUDP
* object. Elaborate the pin expressions as netlists, then connect
* those networks to the pins.
*/
void PGModule::elaborate_sudp_(Design*des, PUdp*udp, const string&path) const
{
const string my_name = path+"."+get_name();
NetUDP*net = new NetUDP(my_name, udp->ports.count(), udp->sequential);
net->set_attributes(udp->attributes);
/* Run through the pins, making netlists for the pin
expressions and connecting them to the pin in question. All
of this is independent of the nature of the UDP. */
for (unsigned idx = 0 ; idx < net->pin_count() ; idx += 1) {
if (pin(idx) == 0)
continue;
NetNet*sig = pin(idx)->elaborate_net(des, path, 1, 0, 0, 0);
if (sig == 0) {
cerr << "internal error: Expression too complicated "
"for elaboration:" << *pin(idx) << endl;
continue;
}
connect(sig->pin(0), net->pin(idx));
// Delete excess holding signal.
if (NetTmp*tmp = dynamic_cast<NetTmp*>(sig))
delete tmp;
}
/* Build up the truth table for the netlist from the input
strings. */
for (unsigned idx = 0 ; idx < udp->tinput.count() ; idx += 1) {
string input = string("") + udp->tcurrent[idx] + udp->tinput[idx];
net->set_table(input, udp->toutput[idx]);
}
net->cleanup_table();
switch (udp->initial) {
case verinum::V0:
net->set_initial('0');
break;
case verinum::V1:
net->set_initial('1');
break;
case verinum::Vx:
case verinum::Vz:
net->set_initial('x');
break;
}
// All done. Add the object to the design.
des->add_node(net);
}
void PGModule::elaborate(Design*des, const string&path) const
{
// Look for the module type
map<string,Module*>::const_iterator mod = modlist->find(type_);
if (mod != modlist->end()) {
elaborate_mod_(des, (*mod).second, path);
return;
}
// Try a primitive type
map<string,PUdp*>::const_iterator udp = udplist->find(type_);
if (udp != udplist->end()) {
if ((*udp).second->sequential)
elaborate_sudp_(des, (*udp).second, path);
else
elaborate_cudp_(des, (*udp).second, path);
return;
}
cerr << get_line() << ": internal error: Unknown module type: " <<
type_ << endl;
}
void PGModule::elaborate_scope(Design*des, NetScope*sc) const
{
// Look for the module type
map<string,Module*>::const_iterator mod = modlist->find(type_);
if (mod != modlist->end()) {
elaborate_scope_mod_(des, (*mod).second, sc);
return;
}
// Try a primitive type
map<string,PUdp*>::const_iterator udp = udplist->find(type_);
if (udp != udplist->end())
return;
cerr << get_line() << ": error: Unknown module type: " << type_ << endl;
des->errors += 1;
}
/*
* The concatenation is also OK an an l-value. This method elaborates
* it as a structural l-value.
*/
NetNet* PEConcat::elaborate_lnet(Design*des, const string&path) const
{
svector<NetNet*>nets (parms_.count());
unsigned pins = 0;
unsigned errors = 0;
if (repeat_) {
cerr << get_line() << ": sorry: I do not know how to"
" elaborate repeat concatenation nets." << endl;
return 0;
}
/* Elaborate the operands of the concatenation. */
for (unsigned idx = 0 ; idx < nets.count() ; idx += 1) {
nets[idx] = parms_[idx]->elaborate_lnet(des, path);
if (nets[idx] == 0)
errors += 1;
else
pins += nets[idx]->pin_count();
}
/* If any of the sub expressions failed to elaborate, then
delete all those that did and abort myself. */
if (errors) {
for (unsigned idx = 0 ; idx < nets.count() ; idx += 1) {
if (nets[idx]) delete nets[idx];
}
des->errors += 1;
return 0;
}
/* Make the temporary signal that connects to all the
operands, and connect it up. Scan the operands of the
concat operator from least significant to most significant,
which is opposite from how they are given in the list. */
NetNet*osig = new NetNet(0, des->local_symbol(path),
NetNet::IMPLICIT, pins);
pins = 0;
for (unsigned idx = nets.count() ; idx > 0 ; idx -= 1) {
NetNet*cur = nets[idx-1];
for (unsigned pin = 0 ; pin < cur->pin_count() ; pin += 1) {
connect(osig->pin(pins), cur->pin(pin));
pins += 1;
}
}
osig->local_flag(true);
des->add_signal(osig);
return osig;
}
NetProc* Statement::elaborate(Design*des, const string&path) const
{
cerr << "internal error: elaborate: What kind of statement? " <<
typeid(*this).name() << endl;
NetProc*cur = new NetProc;
return cur;
}
NetProc* PAssign::assign_to_memory_(NetMemory*mem, PExpr*ix,
Design*des, const string&path) const
{
NetScope*scope = des->find_scope(path);
assert(scope);
NetExpr*rv = rval()->elaborate_expr(des, scope);
if (rv == 0)
return 0;
assert(rv);
rv->set_width(mem->width());
if (ix == 0) {
cerr << get_line() << ": internal error: No index in lval "
<< "of assignment to memory?" << endl;
return 0;
}
assert(ix);
NetNet*idx = ix->elaborate_net(des, path, 0, 0, 0, 0);
assert(idx);
if (rv->expr_width() < mem->width())
rv = pad_to_width(rv, mem->width());
NetAssignMem*am = new NetAssignMem(mem, idx, rv);
am->set_line(*this);
return am;
}
/*
* Elaborate an l-value as a NetNet (it may already exist) and make up
* the part select stuff for where the assignment is going to be made.
*/
NetNet* PAssign_::elaborate_lval(Design*des, const string&path,
unsigned&msb, unsigned&lsb,
NetExpr*&mux) const
{
NetScope*scope = des->find_scope(path);
assert(scope);
/* Get the l-value, and assume that it is an identifier. */
const PEIdent*id = dynamic_cast<const PEIdent*>(lval());
/* If the l-value is not a register, then make a structural
elaboration. Make a synthetic register that connects to the
generated circuit and return that as the l-value. */
if (id == 0) {
NetNet*ll = lval_->elaborate_net(des, path, 0, 0, 0, 0);
if (ll == 0) {
cerr << get_line() << ": Assignment l-value too complex."
<< endl;
return 0;
}
lsb = 0;
msb = ll->pin_count()-1;
mux = 0;
return ll;
}
assert(id);
/* Get the signal referenced by the identifier, and make sure
it is a register. (Wires are not allows in this context. */
NetNet*reg = des->find_signal(path, id->name());
if (reg == 0) {
cerr << get_line() << ": error: Could not match signal ``" <<
id->name() << "'' in ``" << path << "''" << endl;
des->errors += 1;
return 0;
}
assert(reg);
if ((reg->type() != NetNet::REG) && (reg->type() != NetNet::INTEGER)) {
cerr << get_line() << ": error: " << *lval() <<
" is not a register." << endl;
des->errors += 1;
return 0;
}
if (id->msb_ && id->lsb_) {
/* This handles part selects. In this case, there are
two bit select expressions, and both must be
constant. Evaluate them and pass the results back to
the caller. */
verinum*vl = id->lsb_->eval_const(des, path);
if (vl == 0) {
cerr << id->lsb_->get_line() << ": error: "
"Expression must be constant in this context: "
<< *id->lsb_;
des->errors += 1;
return 0;
}
verinum*vm = id->msb_->eval_const(des, path);
if (vl == 0) {
cerr << id->msb_->get_line() << ": error: "
"Expression must be constant in this context: "
<< *id->msb_;
des->errors += 1;
return 0;
}
msb = vm->as_ulong();
lsb = vl->as_ulong();
mux = 0;
} else if (id->msb_) {
/* If there is only a single select expression, it is a
bit select. Evaluate the constant value and treat it
as a part select with a bit width of 1. If the
expression it not constant, then return the
expression as a mux. */
assert(id->lsb_ == 0);
verinum*v = id->msb_->eval_const(des, path);
if (v == 0) {
NetExpr*m = id->msb_->elaborate_expr(des, scope);
assert(m);
msb = 0;
lsb = 0;
mux = m;
} else {
msb = v->as_ulong();
lsb = v->as_ulong();
mux = 0;
}
} else {
/* No select expressions, so presume a part select the
width of the register. */
assert(id->msb_ == 0);
assert(id->lsb_ == 0);
msb = reg->msb();
lsb = reg->lsb();
mux = 0;
}
return reg;
}
NetProc* PAssign::elaborate(Design*des, const string&path) const
{
NetScope*scope = des->find_scope(path);
assert(scope);
/* Catch the case where the lvalue is a reference to a memory
item. These are handled differently. */
do {
const PEIdent*id = dynamic_cast<const PEIdent*>(lval());
if (id == 0) break;
NetNet*net = des->find_signal(path, id->name());
if (net && (net->scope() == scope))
break;
if (NetMemory*mem = des->find_memory(path, id->name()))
return assign_to_memory_(mem, id->msb_, des, path);
} while(0);
/* elaborate the lval. This detects any part selects and mux
expressions that might exist. */
unsigned lsb, msb;
NetExpr*mux;
NetNet*reg = elaborate_lval(des, path, msb, lsb, mux);
if (reg == 0) return 0;
/* If there is a delay expression, elaborate it. */
unsigned long rise_time, fall_time, decay_time;
delay_.eval_delays(des, path, rise_time, fall_time, decay_time);
/* Elaborate the r-value expression. */
assert(rval());
NetExpr*rv;
if (verinum*val = rval()->eval_const(des,path)) {
rv = new NetEConst(*val);
delete val;
} else if (rv = rval()->elaborate_expr(des, scope)) {
/* OK, go on. */
} else {
/* Unable to elaborate expression. Retreat. */
return 0;
}
assert(rv);
/* Try to evaluate the expression, at least as far as possible. */
if (NetExpr*tmp = rv->eval_tree()) {
delete rv;
rv = tmp;
}
NetAssign*cur;
/* Rewrite delayed assignments as assignments that are
delayed. For example, a = #<d> b; becomes:
begin
tmp = b;
#<d> a = tmp;
end
If the delay is an event delay, then the transform is
similar, with the event delay replacing the time delay. It
is an event delay if the event_ member has a value.
This rewriting of the expression allows me to not bother to
actually and literally represent the delayed assign in the
netlist. The compound statement is exactly equivalent. */
if (rise_time || event_) {
string n = des->local_symbol(path);
unsigned wid = reg->pin_count();
rv->set_width(reg->pin_count());
rv = pad_to_width(rv, reg->pin_count());
if (! rv->set_width(reg->pin_count())) {
cerr << get_line() << ": error: Unable to match "
"expression width of " << rv->expr_width() <<
" to l-value width of " << wid << "." << endl;
//XXXX delete rv;
return 0;
}
NetNet*tmp = new NetNet(0, n, NetNet::REG, wid);
tmp->set_line(*this);
des->add_signal(tmp);
/* Generate an assignment of the l-value to the temporary... */
n = des->local_symbol(path);
NetAssign*a1 = new NetAssign(n, des, wid, rv);
a1->set_line(*this);
des->add_node(a1);
for (unsigned idx = 0 ; idx < wid ; idx += 1)