DE10_Combined_MIPS_noMEM contains all VHDL code necessary to implement Adaptive-Hypbrid Redundancy (AHR) MIPS on an FPGA

DE10_Combined_MIPS_wMEM_V2_TESTER contains all VHDL code necessary to simulate AHR MIPS using a VHDL simulator.  This includes test programs to run AHR MIPS.

DE10_TMR_MIPS_noMEM contains all VHDL code necessary to implement Triple Modular Redundancy (TMR) MIPS on an FPGA.

DE10_TMR_MIPS_wMEM_TESTER contains all VHDL code necessary to simulate TMR MIPS using a VHDL simulator.  This includes test programs to run on TMR MIPS.


DE10_TSR_MIPS_noMEM contains all VHDL code necessary to implement Temporal Software Redundancy (TSR) MIPS on an FPGA.  TSR MIPS is identical to Basic MIPS in terms of architecture.  The difference is that TSR MIPS uses programs that incorporate Error Detection by Duplicated Instructions (EDDI).


DE10_TSR_MIPS_wMEM_TESTER contains all VHDL code necessary to TSR MIPS using a VHDL simulator.  This includes test EDDI programs to run on Basic MIPS.

The views expressed in this code are those of the authors, and do not reflect the official policy or position of the United States Air Force, Department of Defense, or the U. S. Government. This document has been approved for public release; distribution unlimited, case numbers 88ABW-2019-4400, 88ABW-2019-5331, and 88ABW-2019-5336, 88ABW-2019-5340.