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Revert "[DAG] getNode() - remove oneuse limit from (zext (trunc (asse…
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…rtzext x))) -> (assertzext x) fold"

This reverts commit 05926a5.

Caused AArch64 crash

 rust-lang#12 0x00007f09eec09181 skipExtensionForVectorMULL(llvm::SDNode*, llvm::SelectionDAG&)
 rust-lang#13 0x00007f09eec08289 llvm::AArch64TargetLowering::LowerMUL(llvm::SDValue, llvm::SelectionDAG&) const
 rust-lang#14 0x00007f09eec1a3fd llvm::AArch64TargetLowering::LowerOperation(llvm::SDValue, llvm::SelectionDAG&) const
 rust-lang#15 0x00007f09dc8586a7 (anonymous namespace)::VectorLegalizer::LowerOperationWrapper(llvm::SDNode*, llvm::SmallVectorImpl<llvm::SDValue>&)
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MaskRay committed Sep 22, 2023
1 parent 2d8d622 commit 4389252
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Showing 4 changed files with 7 additions and 6 deletions.
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -5700,7 +5700,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
if (OpOpcode == ISD::TRUNCATE) {
SDValue OpOp = N1.getOperand(0);
if (OpOp.getValueType() == VT) {
if (OpOp.getOpcode() == ISD::AssertZext) {
if (OpOp.getOpcode() == ISD::AssertZext && N1->hasOneUse()) {
APInt HiBits = APInt::getBitsSetFrom(VT.getScalarSizeInBits(),
N1.getScalarValueSizeInBits());
if (MaskedValueIsZero(OpOp, HiBits)) {
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3 changes: 1 addition & 2 deletions llvm/lib/Target/X86/X86ISelLoweringCall.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2645,8 +2645,7 @@ bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
for (;;) {
// Look through nodes that don't alter the bits of the incoming value.
unsigned Op = Arg.getOpcode();
if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST ||
Op == ISD::AssertZext) {
if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) {
Arg = Arg.getOperand(0);
continue;
}
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2 changes: 2 additions & 0 deletions llvm/test/CodeGen/AArch64/setcc_knownbits.ll
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,8 @@
define i1 @load_bv_v4i8(i1 zeroext %a) {
; CHECK-LABEL: load_bv_v4i8:
; CHECK: // %bb.0:
; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
%b = zext i1 %a to i32
%c = icmp eq i32 %b, 1
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll
Original file line number Diff line number Diff line change
Expand Up @@ -62,9 +62,9 @@ define <vscale x 1 x double> @fma_reassociate(<vscale x 1 x double> %a, <vscale
; CHECK-LABEL: fma_reassociate:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vfmadd.vv v11, v10, v12, v0.t
; CHECK-NEXT: vfmadd.vv v9, v8, v11, v0.t
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: vfmadd.vv v9, v8, v12, v0.t
; CHECK-NEXT: vfmadd.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v8, v11
; CHECK-NEXT: ret
%1 = call fast <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, <vscale x 1 x i1> %m, i32 %vl)
%2 = call fast <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %c, <vscale x 1 x double> %d, <vscale x 1 x i1> %m, i32 %vl)
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