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<div class="document" id="mu0-user-manual">
<h1 class="title">mu0 user manual</h1>
<img alt="mu0.png" class="align-center" src="mu0.png" style="width: 83.0px; height: 90.0px;" />
<table border="1" class="docutils">
<colgroup>
<col width="25%" />
<col width="75%" />
</colgroup>
<tbody valign="top">
<tr><td><strong>Title</strong></td>
<td>mu0 (HDL models and programming tools for the educational
MU0 processor)</td>
</tr>
<tr><td><strong>Author</strong></td>
<td>Nikolaos Kavvadias (C) 2010, 2011, 2012, 2013, 2014,
2015</td>
</tr>
<tr><td><strong>Contact</strong></td>
<td><a class="reference external" href="mailto:nikos@nkavvadias.com">nikos@nkavvadias.com</a></td>
</tr>
<tr><td><strong>Website</strong></td>
<td><a class="reference external" href="http://www.nkavvadias.com">http://www.nkavvadias.com</a></td>
</tr>
<tr><td><strong>Release Date</strong></td>
<td>29 November 2014</td>
</tr>
<tr><td><strong>Version</strong></td>
<td>0.0.4</td>
</tr>
<tr><td><strong>Rev. history</strong></td>
<td> </td>
</tr>
<tr><td><strong>v0.0.4</strong></td>
<td><p class="first">2014-11-29</p>
<p class="last">Added project logo in README.</p>
</td>
</tr>
<tr><td><strong>v0.0.3</strong></td>
<td><p class="first">2014-11-19</p>
<p class="last">Extended the compiler/assembler to automatically produce
ArchC hexadecimal files; add non-interactive mode.</p>
</td>
</tr>
<tr><td><strong>v0.0.2</strong></td>
<td><p class="first">2014-11-18</p>
<p class="last">Added more test programs/listings; minor documentation
update.</p>
</td>
</tr>
<tr><td><strong>v0.0.1</strong></td>
<td><p class="first">2014-11-17</p>
<p class="last">Added preliminary version of the ArchC model for the
processor. This models a byte-addressable version of MU0.</p>
</td>
</tr>
<tr><td><strong>v0.0.0</strong></td>
<td><p class="first">2014-11-14</p>
<p class="last">Initial release.</p>
</td>
</tr>
</tbody>
</table>
<div class="section" id="introduction">
<h1>1. Introduction</h1>
<p>The <tt class="docutils literal">mu0</tt> is an educational computer taught at the University of Manchester
(<a class="reference external" href="http://www.cs.man.ac.uk/~pjj/cs1011/mu0_l1.html">CS1011_MU0</a> and <a class="citation-reference" href="#furber" id="id1">[Furber]</a>). It is based on the <a class="reference external" href="http://en.wikipedia.org/wiki/Manchester_Small-Scale_Experimental_Machine">SSEM</a> computer which was one of
the first computers every built - at the University (and is considered, along
with the Harvard Mark 1 to be the first real computer).</p>
<p>The MU0 is used to illustrate basic programming concepts, and encourages
thorough design due to the fact it only has 8 useful instructions (including a
halting/stop instruction), albeit there is available opcode space for an
additional eight instructions.</p>
<p>The processor can directly address 4096 words, each 16 bits long. Each word is
capable of storing one fixed length command, which consists of 4 bits of opcode
and 12 bits of operand, in all cases except the STOP command which takes no
operand.</p>
<p>The only internal register is known as the accumulator (<tt class="docutils literal">ACC</tt>) and this is
where all processing must take place. It is 16 bits long, and is where both
inputs to calculations and results must be stored. In total, an MU0 processor
has three registers:</p>
<ul class="simple">
<li><tt class="docutils literal">ACC</tt>: the accumulator</li>
<li><tt class="docutils literal">PC</tt>: the program counter</li>
<li><tt class="docutils literal">IR</tt>: the instruction register.</li>
</ul>
<p>The following table illustrates the instruction set of the MU0.</p>
<table border="1" class="docutils">
<colgroup>
<col width="12%" />
<col width="19%" />
<col width="37%" />
<col width="32%" />
</colgroup>
<tbody valign="top">
<tr><td>Opcode</td>
<td>Instruction</td>
<td>Effect</td>
<td>Syntax variant (tools)</td>
</tr>
<tr><td><tt class="docutils literal">0000</tt></td>
<td><tt class="docutils literal">LDA S</tt></td>
<td><tt class="docutils literal">ACC = mem[S]</tt></td>
<td><tt class="docutils literal">ACC<= [S]</tt></td>
</tr>
<tr><td><tt class="docutils literal">0001</tt></td>
<td><tt class="docutils literal">STO S</tt></td>
<td><tt class="docutils literal">mem[S] = ACC</tt></td>
<td><tt class="docutils literal">ACC>= [S]</tt></td>
</tr>
<tr><td><tt class="docutils literal">0010</tt></td>
<td><tt class="docutils literal">ADD S</tt></td>
<td><tt class="docutils literal">ACC += mem[S]</tt></td>
<td><tt class="docutils literal">ACC+ [S]</tt></td>
</tr>
<tr><td><tt class="docutils literal">0011</tt></td>
<td><tt class="docutils literal">SUB S</tt></td>
<td><tt class="docutils literal">ACC <span class="pre">-=</span> mem[S]</tt></td>
<td><tt class="docutils literal">ACC- [S]</tt></td>
</tr>
<tr><td><tt class="docutils literal">0100</tt></td>
<td><tt class="docutils literal">JMP S</tt></td>
<td><tt class="docutils literal">pc = S</tt></td>
<td><tt class="docutils literal">PC<= S</tt></td>
</tr>
<tr><td><tt class="docutils literal">0101</tt></td>
<td><tt class="docutils literal">JGE S</tt></td>
<td><tt class="docutils literal">if <span class="pre">ACC>=0</span> pc = S</tt></td>
<td><tt class="docutils literal">IF+VE PC<= S</tt></td>
</tr>
<tr><td><tt class="docutils literal">0110</tt></td>
<td><tt class="docutils literal">JNE S</tt></td>
<td><tt class="docutils literal">if <span class="pre">ACC!=0</span> pc = S</tt></td>
<td><tt class="docutils literal"><span class="pre">IF!=0</span> PC<= S</tt></td>
</tr>
<tr><td><tt class="docutils literal">0111</tt></td>
<td><tt class="docutils literal">STP</tt></td>
<td><tt class="docutils literal">stop</tt></td>
<td><tt class="docutils literal">STP</tt></td>
</tr>
</tbody>
</table>
<p>This distribution provides the following:</p>
<ul class="simple">
<li>Behavioral VHDL and Verilog HDL models for the <tt class="docutils literal">mu0</tt>.</li>
<li>ArchC functional simulation model for the <tt class="docutils literal">mu0</tt>.</li>
<li>Compiler (assembler) and simulator/debugger for the <tt class="docutils literal">mu0</tt> based on the
original work of user <tt class="docutils literal">benjy</tt>: <a class="reference external" href="http://everything2.com/title/MU0">http://everything2.com/title/MU0</a></li>
<li>Scripts for running VHDL simulations with GHDL or Modelsim.</li>
<li>Scripts for running Verilog HDL simulations with Icarus Verilog or Modelsim.</li>
<li>Various test files (<tt class="docutils literal">*.mu0</tt>, <tt class="docutils literal">*.lst</tt>, <tt class="docutils literal">*.hex</tt>).</li>
</ul>
<p>Future releases will contain adapted synthesizable models, synthesis scripts
for Xilinx ISE/Vivado and <a class="reference external" href="http://clifford.at/yosys/">YOSYS</a> and more.</p>
<p>The original documentation as written by <tt class="docutils literal">benjy</tt> can be found in the <tt class="docutils literal">/doc</tt>
subdirectory in plain text, HTML and PDF formats.</p>
</div>
<div class="section" id="file-listing">
<h1>2. File listing</h1>
<p>The <tt class="docutils literal">mu0</tt> distribution includes the following files:</p>
<table border="1" class="docutils">
<colgroup>
<col width="30%" />
<col width="70%" />
</colgroup>
<tbody valign="top">
<tr><td>/mu0</td>
<td>Top-level directory</td>
</tr>
<tr><td>AUTHORS</td>
<td>List of authors.</td>
</tr>
<tr><td>LICENSE</td>
<td>The license agreement for using <tt class="docutils literal">mu0</tt>.</td>
</tr>
<tr><td>README.rst</td>
<td>This file.</td>
</tr>
<tr><td>README.html</td>
<td>HTML version of README.</td>
</tr>
<tr><td>README.pdf</td>
<td>PDF version of README.</td>
</tr>
<tr><td>VERSION</td>
<td>Current version of the <tt class="docutils literal">mu0</tt> project.</td>
</tr>
<tr><td>mu0.png</td>
<td>PNG image for the <tt class="docutils literal">mu0</tt> project logo.</td>
</tr>
<tr><td>rst2docs.sh</td>
<td>Bash script for generating the HTML and PDF versions.</td>
</tr>
<tr><td>/bench/verilog</td>
<td>Verilog HDL testbench directory</td>
</tr>
<tr><td>mu0_tb.v</td>
<td>Testbench for exercising the Verilog HDL model.</td>
</tr>
<tr><td>/bench/vhdl</td>
<td>VHDL testbench directory</td>
</tr>
<tr><td>mu0_tb.vhd</td>
<td>Testbench for exercising the VHDL model.</td>
</tr>
<tr><td>/doc</td>
<td>Documentation directory</td>
</tr>
<tr><td>mu0-compiler-sim.rst</td>
<td>Detailed documentation on the MU0 assembler and
simulator (authored by user <tt class="docutils literal">benjy</tt>).</td>
</tr>
<tr><td>mu0-compiler-sim.html</td>
<td>HTML version of the above.</td>
</tr>
<tr><td>mu0-compiler-sim.pdf</td>
<td>PDF version of the above.</td>
</tr>
<tr><td>rst2docs.sh</td>
<td>Bash script for generating the HTML and PDF versions.</td>
</tr>
<tr><td>/rtl/verilog</td>
<td>RTL Verilog source code directory for <tt class="docutils literal">mu0</tt></td>
</tr>
<tr><td>mu0_behav.v</td>
<td>Behavioral Verilog HDL model.</td>
</tr>
<tr><td>/rtl/vhdl</td>
<td>RTL VHDL source code directory for <tt class="docutils literal">mu0</tt></td>
</tr>
<tr><td>mu0_behav.vhd</td>
<td>Behavioral VHDL model.</td>
</tr>
<tr><td>/sim/archc</td>
<td>ArchC model files main directory</td>
</tr>
<tr><td>/sim/archc/src</td>
<td>Source directory for the model files</td>
</tr>
<tr><td>mu0.ac</td>
<td>Register and memory model for MU0.</td>
</tr>
<tr><td>mu0_isa.ac</td>
<td>Instruction encodings and assembly formats.</td>
</tr>
<tr><td>mu0_isa.cpp</td>
<td>Instruction behaviors.</td>
</tr>
<tr><td>/sim/archc/test</td>
<td>Tests subdirectory</td>
</tr>
<tr><td>gen-tests.sh</td>
<td>Bash shell script for generating ArchC hexadecimal
application files for the simulator.</td>
</tr>
<tr><td>*.hex</td>
<td>ArchC hexadecimal application files for testing.</td>
</tr>
<tr><td>/sim/rtl_sim</td>
<td>RTL simulation files directory</td>
</tr>
<tr><td>/sim/rtl_sim/bin</td>
<td>RTL simulation scripts directory</td>
</tr>
<tr><td>mu0_behav.mk</td>
<td>Unix/Cygwin makefile for running a GHDL simulation.</td>
</tr>
<tr><td>mu0_behav_verilog.do</td>
<td>Modelsim <tt class="docutils literal">do</tt> macro for running a Verilog
simulation.</td>
</tr>
<tr><td>mu0_behav_vhdl.do</td>
<td>Modelsim <tt class="docutils literal">do</tt> macro for running a VHDL simulation.</td>
</tr>
<tr><td>/sim/rtl_sim/out</td>
<td>Dumps and other useful output from RTL simulation</td>
</tr>
<tr><td>mu0_behavioral.vcd</td>
<td>VCD (Value Change Dump) file from the last
simulation run.</td>
</tr>
<tr><td>/sim/rtl_sim/run</td>
<td>Files for running RTL simulations</td>
</tr>
<tr><td>ghdl.sh</td>
<td>Bash shell script for running a GHDL simulation.</td>
</tr>
<tr><td>iverilog.sh</td>
<td>Bash shell script for running an Icarus Verilog
simulation.</td>
</tr>
<tr><td>load-program.sh</td>
<td>Bash shell script for loading a new program to the
HDL processor model (either Verilog HDL or VHDL).</td>
</tr>
<tr><td>mti-verilog.sh</td>
<td>Bash shell script for running a Modelsim simulation
of the Verilog HDL model.</td>
</tr>
<tr><td>mti-vhdl.sh</td>
<td>Bash shell script for running a Modelsim simulation
of the VHDL model.</td>
</tr>
<tr><td>multiply.lst</td>
<td>Hexadecimal listing generated from
<tt class="docutils literal">multiply.mu0</tt> using the <tt class="docutils literal">mu0</tt> compiler.</td>
</tr>
<tr><td>multiply.mu0</td>
<td>Multiplication test program.</td>
</tr>
<tr><td>odd_even.lst</td>
<td>Hexadecimal listing generated from
<tt class="docutils literal">odd_even.mu0</tt> using the <tt class="docutils literal">mu0</tt> compiler.</td>
</tr>
<tr><td>odd_even.mu0</td>
<td>Test program for finding even numbers in a list.</td>
</tr>
<tr><td>prog.lst</td>
<td>The listing file currently visible to the processor
models. Its contents are preloaded to memory before
simulation starts.</td>
</tr>
<tr><td>test*.lst</td>
<td>Sample test listings.</td>
</tr>
<tr><td>test*.mu0</td>
<td>Sample test programs.</td>
</tr>
<tr><td>/sim/rtl_sim/run</td>
<td>Verilog HDL sources for running RTL simulations</td>
</tr>
<tr><td>/sim/rtl_sim/vhdl</td>
<td>VHDL source files used for running RTL simulations</td>
</tr>
<tr><td>std_logic_textio.vhd</td>
<td>Modified version of a testbench-related package.</td>
</tr>
<tr><td>/sw</td>
<td>Software utilities</td>
</tr>
<tr><td>Makefile</td>
<td>GNU Makefile for building the compiler and debugger.</td>
</tr>
<tr><td>compile_mu0.c</td>
<td>The MU0 compiler (assembler) developed by <tt class="docutils literal">benjy</tt>.</td>
</tr>
<tr><td>execute_mu0.c</td>
<td>The MU0 debugger developed by <tt class="docutils literal">benjy</tt>.</td>
</tr>
</tbody>
</table>
</div>
<div class="section" id="usage">
<h1>3. Usage</h1>
<div class="section" id="build-the-mu0-compiler-and-debugger">
<h2>Build the MU0 compiler and debugger</h2>
<p>Here we assume that the <tt class="docutils literal">/mu0</tt> distribution directory is a subdirectory of the
working directory.</p>
<div class="line-block">
<div class="line"><tt class="docutils literal">$ cd mu0</tt></div>
<div class="line"><tt class="docutils literal">$ cd sw</tt></div>
<div class="line"><tt class="docutils literal">$ make clean ; make ; make tidy</tt></div>
</div>
<p>Now the compiler (<tt class="docutils literal">compile_mu0.exe</tt>) and debugger/simulator
(<tt class="docutils literal">execute_mu0.exe</tt>) have been generated.</p>
</div>
<div class="section" id="compile-an-mu0-application">
<h2>Compile an MU0 application</h2>
<div class="line-block">
<div class="line"><tt class="docutils literal">$ cd <span class="pre">../sim/rtl_sim/run</span></tt></div>
<div class="line"><tt class="docutils literal">$ <span class="pre">../../../sw/compile_mu0.exe</span></tt></div>
</div>
<p>A command-prompt appears which looks like this:</p>
<pre class="literal-block">
COMPILE_MU0 - companion program to EXECUTE_MU0
(C) 1994 Benjy
Please enter source filename >
</pre>
<p>The user can enter the file name of an existing <tt class="docutils literal">*.mu0</tt> assembly program
such as <tt class="docutils literal">multiply.mu0</tt>:</p>
<pre class="literal-block">
Please enter source filename > multiply.mu0
</pre>
<p>In the subsequent prompt, the user should enter the preferred filename for the
listing (hexadecimal file) to be produced:</p>
<pre class="literal-block">
Please enter destination filename > multiply.lst
</pre>
<p>By hitting enter again, two-pass assembly will take place and the produced
listing will be available for loading to the processor model(s).</p>
</div>
<div class="section" id="load-the-program">
<h2>Load the program</h2>
<div class="line-block">
<div class="line"><tt class="docutils literal">$ <span class="pre">./load-program</span> multiply.lst</tt></div>
</div>
<p>The above command copies the produced listing, <tt class="docutils literal">multiply.lst</tt> to <tt class="docutils literal">prog.lst</tt>
which is the name of the listing that both the Verilog HDL and VHDL models
expect to read and load to the processor's memory.</p>
</div>
<div class="section" id="run-verilog-hdl-simulation-using-icarus-verilog">
<h2>Run Verilog HDL simulation using Icarus Verilog</h2>
<p>To run a Verilog HDL simulation using Icarus Verilog, the following script
can be used. As with all simulation scripts, the user will have to edit it
in order to provide the correct path to the tools (Icarus Verilog, GHDL,
Modelsim) for his/her setup.</p>
<div class="line-block">
<div class="line"><tt class="docutils literal">$ ./iverilog.sh</tt></div>
</div>
</div>
<div class="section" id="run-verilog-hdl-simulation-using-modelsim">
<h2>Run Verilog HDL simulation using Modelsim</h2>
<div class="line-block">
<div class="line"><tt class="docutils literal">$ <span class="pre">./mti-verilog.sh</span></tt></div>
</div>
</div>
<div class="section" id="run-vhdl-simulation-using-ghdl">
<h2>Run VHDL simulation using GHDL</h2>
<div class="line-block">
<div class="line"><tt class="docutils literal">$ ./ghdl.sh</tt></div>
</div>
</div>
<div class="section" id="run-vhdl-simulation-using-modelsim">
<h2>Run VHDL simulation using Modelsim</h2>
<div class="line-block">
<div class="line"><tt class="docutils literal">$ <span class="pre">./mti-vhdl.sh</span></tt></div>
</div>
</div>
<div class="section" id="visualize-simulation-waveforms">
<h2>Visualize simulation waveforms</h2>
<p>For both VHDL and Verilog HDL simulations, waveform data are produced in the
VCD format. VCD waveforms can be easily viewed using GTKwave.</p>
<div class="line-block">
<div class="line"><tt class="docutils literal">$ gtkwave <span class="pre">../out/mu0_behavioral.vcd</span></tt></div>
</div>
</div>
</div>
<div class="section" id="archc-model">
<h1>4. ArchC model</h1>
<p>This is the ArchC (<a class="reference external" href="http://www.archc.org">http://www.archc.org</a>) functional simulator model for the
MU0 processor. For the time being, the architecture is modelled as a
byte-addressable, as the careful reader can notice by examining the ArchC
hexadecimal applications files that can be found in <tt class="docutils literal">/mu0/sim/archc/tests</tt>.
If the <tt class="docutils literal">JGE_IS_JGT</tt> preprocessor directive is set, then the behavior of
the jump if positive (<tt class="docutils literal">jge</tt>) instruction is altered to convey the meaning of
jump if (strictly) larger than zero. There is no concensus about the behavior
of this specific instruction, according to various sources on the MU0 processor.</p>
<div class="section" id="building-the-model">
<h2>Building the model</h2>
<p>To generate the interpreted simulator, the <tt class="docutils literal">acsim</tt> executable is ran:</p>
<pre class="literal-block">
$ acsim mu0.ac # (create the simulator)
$ make -f Makefile.archc # (compile)
$ ./mu0.x --load=<file-path> [args] # (run an application)
</pre>
<p>There are two formats recognized for application <file-path>:</p>
<ul class="simple">
<li>ELF binary matching ArchC specifications</li>
<li>hexadecimal text file for ArchC, which has currently been tested.</li>
</ul>
<p>In order to generate the binary utilities port (<tt class="docutils literal">binutils</tt> port), the
<tt class="docutils literal">acbingen.sh</tt> driver script must be used. This should be called as follows:</p>
<pre class="literal-block">
$ acbingen.sh -amu0 -i`pwd`/../mu0-tools/ mu0.ac
</pre>
<p>for generating the <tt class="docutils literal">binutils</tt> port executables. This includes the following
tools:</p>
<ul class="simple">
<li><tt class="docutils literal">addr2line</tt></li>
<li><tt class="docutils literal">ar</tt></li>
<li><tt class="docutils literal">as</tt></li>
<li><tt class="docutils literal"><span class="pre">c++filt</span></tt></li>
<li><tt class="docutils literal">ld</tt></li>
<li><tt class="docutils literal">nm</tt></li>
<li><tt class="docutils literal">objcopy</tt></li>
<li><tt class="docutils literal">objdump</tt></li>
<li><tt class="docutils literal">ranlib</tt></li>
<li><tt class="docutils literal">readelf</tt></li>
<li><tt class="docutils literal">size</tt></li>
<li><tt class="docutils literal">strings</tt></li>
<li><tt class="docutils literal">strip</tt></li>
</ul>
<p>This feature has not yet been tested for the <tt class="docutils literal">mu0</tt> model.</p>
</div>
<div class="section" id="alternative-assembly-syntax">
<h2>Alternative assembly syntax</h2>
<p>The ArchC-based tools support a number of alternative assembly instruction
syntaxes for <tt class="docutils literal">mu0</tt>. The following table summarizes the differences between the
syntax variations.</p>
<table border="1" class="docutils">
<colgroup>
<col width="30%" />
<col width="33%" />
<col width="37%" />
</colgroup>
<tbody valign="top">
<tr><td>Instruction</td>
<td colspan="2">Alternative syntax</td>
</tr>
<tr><td><tt class="docutils literal">lda</tt></td>
<td colspan="2"><tt class="docutils literal">lda imm</tt></td>
</tr>
<tr><td><tt class="docutils literal">sto</tt></td>
<td colspan="2"><tt class="docutils literal">sto imm</tt></td>
</tr>
<tr><td><tt class="docutils literal">add</tt></td>
<td colspan="2"><tt class="docutils literal">add imm</tt></td>
</tr>
<tr><td><tt class="docutils literal">sub</tt></td>
<td colspan="2"><tt class="docutils literal">sub imm</tt></td>
</tr>
<tr><td><tt class="docutils literal">jmp</tt></td>
<td colspan="2"><tt class="docutils literal">jmp imm</tt></td>
</tr>
<tr><td><tt class="docutils literal">jge</tt></td>
<td colspan="2"><tt class="docutils literal">jge imm</tt></td>
</tr>
<tr><td><tt class="docutils literal">jne</tt></td>
<td colspan="2"><tt class="docutils literal">jne imm</tt></td>
</tr>
<tr><td><tt class="docutils literal">stp</tt></td>
<td><tt class="docutils literal">stp</tt></td>
<td><tt class="docutils literal">halt</tt></td>
</tr>
</tbody>
</table>
</div>
</div>
<div class="section" id="prerequisites">
<h1>5. Prerequisites</h1>
<ul>
<li><p class="first">Standard UNIX-based tools (tested with gcc-4.8.1 on MinGW/x86) [optional if
you use Modelsim].</p>
<ul class="simple">
<li>make</li>
<li>bash (shell)</li>
</ul>
<p>For this reason, MinGW (<a class="reference external" href="http://www.mingw.org">http://www.mingw.org</a>) or Cygwin
(<a class="reference external" href="http://sources.redhat.com/cygwin">http://sources.redhat.com/cygwin</a>) are suggested, since POSIX emulation
environments of sufficient completeness.</p>
</li>
<li><p class="first">Icarus Verilog simulator (<a class="reference external" href="http://iverilog.icarus.com/">http://iverilog.icarus.com/</a>).
The Windows version can be downloaded from: <a class="reference external" href="http://bleyer.org/icarus/">http://bleyer.org/icarus/</a></p>
</li>
<li><p class="first">GHDL simulator (<a class="reference external" href="http://ghdl.free.fr">http://ghdl.free.fr</a>) [optional if you use Modelsim].
Provides the <tt class="docutils literal">ghdl</tt> executable (has several Windows versions, with
0.29.1 and 0.31 being the latest). It also installs GTKwave on Windows.
Note that the latest version (0.31) from
<a class="reference external" href="http://sourceforge.net/project/ghdl-updates/">http://sourceforge.net/project/ghdl-updates/</a> does not include GTKwave.</p>
</li>
<li><p class="first">Alternatively, a commercial simulator like Mentor Modelsim
(<a class="reference external" href="http://www.model.com">http://www.model.com</a>) can be used.</p>
</li>
<li><p class="first">ArchC (<a class="reference external" href="http://www.archc.org">http://www.archc.org</a>) installation (tested on Cygwin/Win7-64bit and
Linux) [required only for using the ArchC model]</p>
</li>
</ul>
</div>
<div class="section" id="references">
<h1>References</h1>
<table class="docutils citation" frame="void" id="furber" rules="none">
<colgroup><col class="label" /><col /></colgroup>
<tbody valign="top">
<tr><td class="label"><a class="fn-backref" href="#id1">[Furber]</a></td><td>Stephen Furber, ARM System-on-chip Architecture, 2nd edition, Pearson
Education Limited, 2000.</td></tr>
</tbody>
</table>
</div>
</div>
</body>
</html>