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Code for LCD visualization module (Verilog)

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Name		Name	Last commit message	Last commit date
Latest commit History 12 Commits
Controller.v		Controller.v
Counter.v		Counter.v
Display.v		Display.v
Init.v		Init.v
Main.v		Main.v
README.md		README.md

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LCD_Modules

All Modules of LCD of Balance Project, Digital I, 2013 I

Roberto Felipe Salamanca; Fabian Alejandro Rubiano; Nicolás Malpic Forero.

Universidad Nacional de Colombia 2013

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Code for LCD visualization module (Verilog)

verilog nexys2 lcd-modules

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Verilog 100.0%