[Reverse-engineering] [th05] Masked PI display

As used for the title screen fade-in effect. Another function that
apparently was deliberately written to run not that fast, by blitting
each row individually to the 400th VRAM row just so that it can then
turn on the EGC, perform the *actual* masked blit to the VRAM
destination, and then turn the EGC off before moving to the next now.
The same effect could have entirely been accomplished by copying
graph_pack_put_8() and applying the mask there; it's not like ZUN
didn't know how to modify master.lib…

(See also 44ad3eb) --Nmlgc

th03/formats/pi.h

@@ -1,5 +1,9 @@
 #include "th02/formats/pi.h"
 
+#define PI_MASK_COUNT 4
+#define PI_MASK_H 4
+extern const planar16_t PI_MASKS[PI_MASK_COUNT][PI_MASK_H];
+
 // Like pi_slot_put(), but only displays every second row in the given PI.
 int pascal pi_slot_put_interlace(int x, int y, int slot);
 

th03/formats/pi_slot_put_mask[data].asm

@@ -0,0 +1,22 @@
+public _PI_MASKS
+_PI_MASKS	label word
+; 0
+	dw 00000h
+	dw 01111h
+	dw 00000h
+	dw 04444h
+; 1
+	dw 08888h
+	dw 01111h
+	dw 02222h
+	dw 04444h
+; 2
+	dw 0AAAAh
+	dw 05555h
+	dw 0AAAAh
+	dw 05555h
+; 3
+	dw 0EEEEh
+	dw 07777h
+	dw 0BBBBh
+	dw 0DDDDh

th03_mainl.asm

@@ -1465,7 +1465,7 @@ loc_A2B4:
 		and	ax, 3
 		add	ax, ax
 		add	bx, ax
-		outw2	EGC_MASKREG, [bx+8E2h]
+		outw2	EGC_MASKREG, _PI_MASKS[bx]
 		mov	[bp+var_4], 7D00h
 		mov	[bp+var_2], 0
 		jmp	short loc_A31E
@@ -5798,38 +5798,7 @@ include th03/snd/se_priority[data].asm
 		db  30h	; 0
 		db    0
 aOver_pi	db 'over.pi',0
-		db 0
-		db    0
-		db  11h
-		db  11h
-		db    0
-		db    0
-		db  44h	; D
-		db  44h	; D
-		db  88h
-		db  88h
-		db  11h
-		db  11h
-		db  22h	; "
-		db  22h	; "
-		db  44h	; D
-		db  44h	; D
-		db 0AAh	; ｪ
-		db 0AAh	; ｪ
-		db  55h	; U
-		db  55h	; U
-		db 0AAh	; ｪ
-		db 0AAh	; ｪ
-		db  55h	; U
-		db  55h	; U
-		db 0EEh
-		db 0EEh
-		db  77h	; w
-		db  77h	; w
-		db 0BBh
-		db 0BBh
-		db 0DDh
-		db 0DDh
+include th03/formats/pi_slot_put_mask[data].asm
 		db  20h
 		db  20h
 		db    0

th04_maine.asm

@@ -548,7 +548,7 @@ loc_A3F7:
 		and	ax, 3
 		add	ax, ax
 		add	bx, ax
-		outw2	EGC_MASKREG, [bx+60Ch]
+		outw2	EGC_MASKREG, _PI_MASKS[bx]
 		mov	[bp+var_4], 7D00h
 		mov	[bp+var_2], 0
 		jmp	short loc_A461
@@ -5166,38 +5166,7 @@ include th04/hardware/grppsafx[data].asm
 include th03/snd/se_state[data].asm
 include th04/bgimage[data].asm
 include th03/formats/cdg[data].asm
-		db    0
-		db    0
-		db  11h
-		db  11h
-		db    0
-		db    0
-		db  44h	; D
-		db  44h	; D
-		db  88h
-		db  88h
-		db  11h
-		db  11h
-		db  22h	; "
-		db  22h	; "
-		db  44h	; D
-		db  44h	; D
-		db 0AAh	; ｪ
-		db 0AAh	; ｪ
-		db  55h	; U
-		db  55h	; U
-		db 0AAh	; ｪ
-		db 0AAh	; ｪ
-		db  55h	; U
-		db  55h	; U
-		db 0EEh
-		db 0EEh
-		db  77h	; w
-		db  77h	; w
-		db 0BBh	; ｻ
-		db 0BBh	; ｻ
-		db 0DDh
-		db 0DDh
+include th03/formats/pi_slot_put_mask[data].asm
 		db  88h
 		db  88h
 		db    0

th05/formats/pi.h

@@ -1,3 +1,10 @@
 #include "th03/formats/pi.h"
 
 int pascal pi_slot_free(int slot);
+
+// Like pi_slot_put() and pi_slot_put_quarter(), but applying the mask with
+// the given ID while blitting.
+int pascal pi_slot_put_mask(int x, int y, int slot, int mask_id);
+int pascal pi_slot_put_quarter_mask(
+	int x, int y, int slot, int quarter, int mask_id
+);

th05/formats/pi_slot_put_mask.asm

@@ -0,0 +1,176 @@
+public PI_SLOT_PUT_MASK
+pi_slot_put_mask	proc far
+@@mask_id	= word ptr  6
+@@slot	= word ptr  8
+@@y	= word ptr  0Ah
+@@x	= word ptr  0Ch
+
+	push	bp
+	mov	bp, sp
+	push	si
+	push	di
+	mov	si, [bp+@@slot]
+	mov	di, si
+	shl	si, 2
+	les	si, _pi_slot_buffers[si]
+	assume es:nothing
+	imul	di, size PiHeader
+	push	[bp+@@x]
+	push	[bp+@@y]
+	mov	ax, _pi_slot_headers._xsize[di]
+	push	ax
+	shr	ax, 1
+	push	ax
+	mov	di, _pi_slot_headers._ysize[di]
+	mov	ax, [bp+@@mask_id]
+	call	pi_slot_put_mask_rowloop
+	pop	di
+	pop	si
+	pop	bp
+	retf	8
+pi_slot_put_mask	endp
+
+; ---------------------------------------------------------------------------
+
+public PI_SLOT_PUT_QUARTER_MASK
+pi_slot_put_quarter_mask	proc far
+
+@@mask_id	= word ptr  6
+@@quarter	= byte ptr  8
+@@slot	= word ptr  0Ah
+@@y	= word ptr  0Ch
+@@x	= word ptr  0Eh
+
+	push	bp
+	mov	bp, sp
+	push	si
+	push	di
+	xor	ax, ax
+	xor	dx, dx
+	mov	si, [bp+@@slot]
+	mov	cl, [bp+@@quarter]
+	test	cl, 1
+	jz	short @@bottom_quarter?
+	mov	ax, 160
+
+@@bottom_quarter?:
+	test	cl, 2
+	jz	short @@put
+	mov	dx, ((640 * 200) / 2) / 16
+
+@@put:
+	shl	si, 2
+	les	si, _pi_slot_buffers[si]
+	add	si, ax
+	mov	ax, es
+	add	ax, dx
+	mov	es, ax
+	assume es:nothing
+	mov	di, 200
+	push	[bp+@@x]
+	push	[bp+@@y]
+	push	320
+	push	320
+	mov	ax, [bp+@@mask_id]
+	call	pi_slot_put_mask_rowloop
+	pop	di
+	pop	si
+	pop	bp
+	retf	0Ah
+pi_slot_put_quarter_mask	endp
+	even
+
+; ---------------------------------------------------------------------------
+
+; void pascal pi_slot_put_mask_rowloop(
+;	int mask_id<ax>,
+;	void far *pi_buf<es:si>,
+;	int h<di>,
+;	int x, int y, int w, size_t stride_packed
+; );
+pi_slot_put_mask_rowloop	proc near
+@@stride_packed	= word ptr [bp+2]
+@@w	= word ptr [bp+4]
+@@y	= word ptr [bp+6]
+@@x	= word ptr [bp+8]
+@@mask_id equ ax
+@@h equ di
+
+TEMP_ROW = RES_Y
+
+	shl	@@mask_id, 3
+	add	@@mask_id, offset _PI_MASKS
+	mov	_pi_mask_ptr, @@mask_id
+	mov	bp, sp
+	mov	dx, @@x
+	shr	dx, 3
+	mov	ax, @@y
+	shl	ax, 6
+	add	dx, ax
+	shr	ax, 2
+	add	dx, ax
+	mov	_pi_put_mask_vram_offset, dx
+	mov	_pi_mask_y, 0
+
+@@put_row:
+	push	es
+	call	graph_pack_put_8_noclip pascal, 0, TEMP_ROW, es, si, @@w
+	push	ds
+	push	@@h
+	push	si
+	mov	di, _pi_put_mask_vram_offset
+	add	_pi_put_mask_vram_offset, ROW_SIZE
+	cmp	_pi_put_mask_vram_offset, (ROW_SIZE * RES_Y)
+	jb	short @@next_row
+	sub	_pi_put_mask_vram_offset, (ROW_SIZE * RES_Y)
+
+@@next_row:
+	call	pi_egc_mask
+	mov	ax, GRAM_400
+	mov	es, ax
+	assume es:nothing
+	mov	ds, ax
+	assume ds:nothing
+	mov	si, (ROW_SIZE * TEMP_ROW)
+	mov	cx, @@w
+	shr	cx, 4
+	rep movsw
+	call	egc_off
+	pop	si
+	pop	@@h
+	pop	ds
+	assume ds:_DATA
+	pop	es
+	assume es:nothing
+	add	si, @@stride_packed
+	mov	ax, si
+	shr	ax, 4
+	mov	dx, es
+	add	dx, ax
+	mov	es, dx
+	and	si, 0Fh
+	dec	@@h
+	jnz	short @@put_row
+	retn	8
+pi_slot_put_mask_rowloop	endp
+
+
+; ---------------------------------------------------------------------------
+
+
+pi_egc_mask	proc near
+	call	egc_on
+	outw2	EGC_ACTIVEPLANEREG, 0FFF0h
+	egc_selectpat
+	egc_setrop	EGC_COMPAREREAD or EGC_WS_PATREG or EGC_RL_MEMREAD
+	outw2	EGC_ADDRRESSREG, 0
+	outw2	EGC_BITLENGTHREG, 0Fh
+	mov	bx, _pi_mask_ptr
+	mov	ax, _pi_mask_y
+	and	ax, 3
+	shl	ax, 1
+	add	bx, ax
+	outw2	EGC_MASKREG, [bx]
+	inc	_pi_mask_y
+	retn
+pi_egc_mask	endp

th05/formats/pi_slot_put_mask[bss].asm

@@ -0,0 +1,4 @@
+public _pi_mask_ptr, _pi_mask_y, _pi_put_mask_vram_offset
+_pi_mask_ptr	dw ?
+_pi_mask_y	dw ?
+_pi_put_mask_vram_offset	dw ?