rtl: Fix CRC E bit generation

According to the spec, the CRC E bits are 1=OK, 0=Error and they must also be transmitted as 0 if RX synchronization is not achieved. To stay consistent everywhere, the status reported in the RX BD status, the bits are also defined as 1=OK, 0=Error and the doc is updated to reflect that. This fixes issue OS#4661 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
no2fpga · Sep 5, 2020 · 26d99a8 · 26d99a8
1 parent bd2555b
commit 26d99a8
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Showing 3 changed files with 6 additions and 3 deletions.
diff --git a/doc/mem-map.md b/doc/mem-map.md
@@ -75,6 +75,9 @@ filled with a multiframe by the E1 core.
   * `c0` : CRC status for sub-multi-frame 0
   * `mf` : Multi-Frame address
 
+Note that just as is the case in the E1 data stream, the CRC
+status is `1` = CRC OK and `0` = CRC error.
+
 
 TX
 --

diff --git a/rtl/e1_rx.v b/rtl/e1_rx.v
@@ -198,9 +198,9 @@ module e1_rx #(
 		// Track the CRC status of the two SMF
 	always @(posedge clk or posedge rst)
 		if (rst)
-			bd_crc_e <= 2'b00;
+			bd_crc_e <= 2'b11;
 		else
-			bd_crc_e <= (bd_done) ? 2'b00 : (bd_crc_e | {
+			bd_crc_e <= (bd_done) ? 2'b11 : (bd_crc_e & ~{
 				df_valid & df_err_crc &  df_frame[3],	// CRC error in second SMF
 				df_valid & df_err_crc & ~df_frame[3]	// CRC error in first SMF
 			});

diff --git a/rtl/e1_wb.v b/rtl/e1_wb.v
@@ -416,7 +416,7 @@ module e1_wb #(
 
 	// Auto E-bit tracking
 	always @(posedge clk)
-		tx_crc_e_auto <= (bdtx_done ? 2'b00 : tx_crc_e_auto) | (bdrx_done ? bdrx_crc_e : 2'b00);
+		tx_crc_e_auto <= (bdtx_done ? {2{rx_aligned}} : tx_crc_e_auto) & (bdrx_done ? bdrx_crc_e : 2'b11);
 
 	// BD FIFO interface
 	assign bdtx_mf    =  bti_do[MFW-1:0];