TST: Add CPU Dispatch test for RISC-V Vector Extenson.

numpy · Apr 22, 2024 · 86a557d · 86a557d
1 parent 3c09f16
commit 86a557d
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Showing 3 changed files with 20 additions and 2 deletions.
diff --git a/numpy/_core/meson.build b/numpy/_core/meson.build
@@ -728,7 +728,7 @@ _umath_tests_mtargets = mod_features.multi_targets(
     AVX2, SSE41, SSE2,
     ASIMDHP, ASIMD, NEON,
     VSX3, VSX2, VSX,
-    VXE, VX,
+    VXE, VX, RVV,
   ],
   baseline: CPU_BASELINE,
   prefix: 'NPY_',

diff --git a/numpy/_core/tests/test_cpu_dispatcher.py b/numpy/_core/tests/test_cpu_dispatcher.py
@@ -12,7 +12,7 @@ def test_dispatcher():
         "SSE2", "SSE41", "AVX2",
         "VSX", "VSX2", "VSX3",
         "NEON", "ASIMD", "ASIMDHP",
-        "VX", "VXE"
+        "VX", "VXE", "RVV"
     )
     highest_sfx = "" # no suffix for the baseline
     all_sfx = []

diff --git a/numpy/_core/tests/test_cpu_features.py b/numpy/_core/tests/test_cpu_features.py
@@ -405,3 +405,21 @@ def load_flags(self):
                 # if the kernel reports any one of the following ARM8 features.
                 ASIMD=("AES", "SHA1", "SHA2", "PMULL", "CRC32")
             )
+
+
+is_riscv = re.match("^riscv(64|32)", machine, re.IGNORECASE)
+@pytest.mark.skipif(not is_linux or not is_riscv, reason="Only for Linux and RISC-V")
+class Test_RISCV_Features(AbstractTest):
+    features = ["RVV"]
+
+    def load_flags(self):
+        isa = self.get_cpuinfo_item("isa")
+        rv_flags = [s.strip() for s in list(isa)[0][4:].split('_')]
+        values = values.union([ch for ch in rv_flags[0].upper()])
+        for s in rv_flags[1:]:
+            values = values.union([s.upper()])
+        self.features_flags = values
+        if 'V' in values:
+            self.features_map = dict(
+                RVV="V"
+            )