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adding language verilog #490 #789

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merged 3 commits into from
Oct 3, 2022
Merged

adding language verilog #490 #789

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2c2d3d1
adding language verilog #490
atluft Oct 3, 2022
6295069
Update languages.yaml
atluft Oct 3, 2022
45c579a
more v straightening and updated chip value
atluft Oct 3, 2022
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28 changes: 28 additions & 0 deletions languages.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -2331,6 +2331,34 @@ Vala:
- magenta
- white
chip: '#A56DE2'
Verilog:
type: programming
ascii: |
{0} _.._ _.._ _.._
{0} _.._ _.._ _.._
{0} _.._ _.._ _.._
{0} _......................_
{0} _.{1} ----- ----- {0}._
{0} _..._.{1} --- --- {0}._..._
{0} _..._.{1} --- --- {0}._..._
{0} _.{1} --- --- {0}._
{0} _.{1} --- --- {0}._
{0} _..._.{1} --- --- {0}._..._
{0} _..._.{1} --- --- {0}._..._
{0} _.{1} --- --- {0}._
{0} _.{1} -- -- {0}._
{0} _..._.{1} ----- {0}._..._
{0} _..._.{1} --- {0}._..._
{0} _.{1} - {0}.._
{0} _......................_
{0} _.._ _.._ _.._
{0} _.._ _.._ _.._
{0} _.._ _.._ _.._
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colors:
ansi:
- white
- magenta
chip: '#C5C2FA'
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Vhdl:
type: programming
ascii: |
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