MSP430 all USCI. TI Makefiles with msp430-tools upload

.hgignore

@@ -0,0 +1,2 @@
+/.*\.o$
+/.*\.obj$

csrc/u8g_com_msp430_hw_spi.c

@@ -48,25 +48,81 @@
 #endif
 #define F_SPI  1000000UL
 
-#define U8G_USE_USCIA2	1
-#define U8G_USE_USCIA3	2
-#define U8G_USE_USCIB0	3
+#define U8G_USE_USCIA0	1
+#define U8G_USE_USCIB0	2
+#define U8G_USE_USCIA1	3
+#define U8G_USE_USCIB1	4
+#define U8G_USE_USCIA2	5
+#define U8G_USE_USCIB2	6
+#define U8G_USE_USCIA3	7
+#define U8G_USE_USCIB3	8
+
 #ifndef U8G_USE_USCI
 #define U8G_USE_USCI	U8G_USE_USCIB0
 #endif
 
+#if U8G_USE_USCI == 1
+#define UCTXBUF UCA0TXBUF
+#define UCSTAT  UCA0STAT
+#define UCCTL0  UCA0CTL0
+#define UCCTL1  UCA0CTL1
+#define UCBR0   UCA0BR0
+#define UCBR1   UCA0BR1
+#elif U8G_USE_USCI == 2
+#define UCTXBUF UCB0TXBUF
+#define UCSTAT  UCB0STAT
+#define UCCTL0  UCB0CTL0
+#define UCCTL1  UCB0CTL1
+#define UCBR0   UCB0BR0
+#define UCBR1   UCB0BR1
+#elif U8G_USE_USCI == 3
+#define UCTXBUF UCA1TXBUF
+#define UCSTAT  UCA1STAT
+#define UCCTL0  UCA1CTL0
+#define UCCTL1  UCA1CTL1
+#define UCBR0   UCA1BR0
+#define UCBR1   UCA1BR1
+#elif U8G_USE_USCI == 4
+#define UCTXBUF UCB1TXBUF
+#define UCSTAT  UCB1STAT
+#define UCCTL0  UCB1CTL0
+#define UCCTL1  UCB1CTL1
+#define UCBR0   UCB1BR0
+#define UCBR1   UCB1BR1
+#elif U8G_USE_USCI == 5
+#define UCTXBUF UCA2TXBUF
+#define UCSTAT  UCA2STAT
+#define UCCTL0  UCA2CTL0
+#define UCCTL1  UCA2CTL1
+#define UCBR0   UCA2BR0
+#define UCBR1   UCA2BR1
+#elif U8G_USE_USCI == 6
+#define UCTXBUF UCB2TXBUF
+#define UCSTAT  UCB2STAT
+#define UCCTL0  UCB2CTL0
+#define UCCTL1  UCB2CTL1
+#define UCBR0   UCB2BR0
+#define UCBR1   UCB2BR1
+#elif U8G_USE_USCI == 7
+#define UCTXBUF UCA3TXBUF
+#define UCSTAT  UCA3STAT
+#define UCCTL0  UCA3CTL0
+#define UCCTL1  UCA3CTL1
+#define UCBR0   UCA3BR0
+#define UCBR1   UCA3BR1
+#elif U8G_USE_USCI == 8
+#define UCTXBUF UCB3TXBUF
+#define UCSTAT  UCB3STAT
+#define UCCTL0  UCB3CTL0
+#define UCCTL1  UCB3CTL1
+#define UCBR0   UCB3BR0
+#define UCBR1   UCB3BR1
+#endif
+
 static uint8_t u8g_msp430_spi_out(uint8_t data)
 {
-#if U8G_USE_USCI == U8G_USE_USCIB0
-  UCB0TXBUF = data;
-  while ((UCB0STAT&UCBUSY));
-#elif U8G_USE_USCI == U8G_USE_USCIA2
-  UCA2TXBUF = data;
-  while ((UCA2STAT&UCBUSY));
-#elif U8g_USE_USCI == U8G_USE_USCIA3
-  UCA3TXBUF = data;
-  while ((UCA3STAT&UCBUSY));
-#endif
+  UCTXBUF = data;
+  while ((UCSTAT&UCBUSY));
 }
 
 uint8_t u8g_com_msp430_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr)
@@ -82,33 +138,12 @@ uint8_t u8g_com_msp430_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void
  	 * may not be required on other MCU's - should be handled
  	 * by a low level u8g_SetPinAlternate(pin_number)...
  	 */
-#if U8G_USE_USCI == U8G_USE_USCIB0
-      P2SEL |= BIT1|BIT3;                       // Assign P2.3 to UCB0CLK and P2.1 UCB0SIMO
-      UCB0CTL1 |= UCSWRST;                      // **Put state machine in reset**
-      UCB0CTL0 |= UCMST|UCSYNC|UCCKPL|UCMSB;    // 3-pin, 8-bit SPI master Clock polarity high, MSB
-      UCB0CTL1 |= UCSSEL_2;                     // SMCLK
-      UCB0BR0 = (unsigned char)(F_CPU/F_SPI);   // 
-      UCB0BR1 = 0;                              //
-      UCB0CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**
-#elif U8G_USE_USCI == U8G_USE_USCIA2
-      P9SEL |= BIT0|BIT4;                     // Assign P9.0 to UCA2CLK and P9.4 UCA2SIMO
-      UCA2CTL1 |= UCSWRST;                      // **Put state machine in reset**
-      UCA2CTL0 |= UCMST|UCSYNC|UCCKPL|UCMSB;    // 3-pin, 8-bit SPI master Clock polarity high, MSB
-      UCA2CTL1 |= UCSSEL_2;                     // SMCLK
-      UCA2BR0 = (unsigned char)(F_CPU/F_SPI);   //
-      UCA2BR1 = 0;                              //
-      UCA2CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**
-#elif U8G_USE_USCI == U8G_USE_USCIA3
-      P10SEL |= BIT0|BIT4;                     // Assign P10.0 to UCA3CLK and P10.4 UCA3SIMO
-      UCA3CTL1 |= UCSWRST;                      // **Put state machine in reset**
-      UCA3CTL0 |= UCMST|UCSYNC|UCCKPL|UCMSB;    // 3-pin, 8-bit SPI master Clock polarity high, MSB
-      UCA3CTL1 |= UCSSEL_2;                     // SMCLK
-      UCA3BR0 = (unsigned char)(F_CPU/F_SPI);   //
-      UCA3BR1 = 0;                              //
-      UCA3CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**
-#else
-#error "Setup SPI failed!"
-#endif
+      UCCTL1 |= UCSWRST;                      // **Put state machine in reset**
+      UCCTL0 |= UCMST|UCSYNC|UCCKPL|UCMSB;    // 3-pin, 8-bit SPI master Clock polarity high, MSB
+      UCCTL1 |= UCSSEL_2;                     // SMCLK
+      UCBR0 = (unsigned char)(F_CPU/F_SPI);   // 
+      UCBR1 = 0;                              //
+      UCCTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**
       u8g_SetPILevel(u8g, U8G_PI_CS, 1);
       u8g_SetPILevel(u8g, U8G_PI_A0, 1);
       u8g_SetPILevel(u8g, U8G_PI_RESET, 1);

sys/msp430/chess/Makefile.ti

@@ -0,0 +1,128 @@
+#
+#   Makefile for TI Compiler
+#
+#   Universal 8bit Graphics Library
+#   
+#   Copyright (c) 2012, olikraus@gmail.com
+#   All rights reserved.
+# 
+#   Redistribution and use in source and binary forms, with or without modification, 
+#   are permitted provided that the following conditions are met:
+# 
+#   * Redistributions of source code must retain the above copyright notice, this list 
+#     of conditions and the following disclaimer.
+#     
+#   * Redistributions in binary form must reproduce the above copyright notice, this 
+#     list of conditions and the following disclaimer in the documentation and/or other 
+#     materials provided with the distribution.
+# 
+#   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 
+#   CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
+#   INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
+#   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 
+#   CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+#   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+#   NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 
+#   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
+#   CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
+#   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+#   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
+#   ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+#
+# 	Features
+#		- upload
+#		- create exe from library
+#		- create assembler listing (.dis)
+#
+#	Limitations
+#		- only C-files supported
+#		- no automatic dependency checking (call 'make clean' if any .h files are changed)
+#
+#	Targets:
+#		make
+#			create hex file, no upload
+#		make upload
+#			create and upload hex file
+#		make clean
+#			delete all generated files
+#
+#  Note:
+#  	Display list make database: make -p -f/dev/null | less
+
+#================================================
+# Project Information
+TARGETNAME = u8g_chess
+DMCU:=__MSP430F5529__
+F_CPU:=16000000
+U8GDIR = ../../../csrc/
+FONTDIR = ../../../sfntsrc/
+
+
+#================================================
+# System/Environment Information
+TIPATH:=/usr/local/ti/ccsv6
+MSP430COMP:=msp430_4.3.3
+TOOLSPATH:=$(TIPATH)/tools/compiler/$(MSP430COMP)
+MSP4305XXLIB:=$(TIPATH)/ccs_base/msp430/lib/5xx_6xx_FRxx
+
+# Add proper arguments for TI HEX tool
+MSP430HEX:=$(TOOLSPATH)/bin/hex430 --memwidth=8 --romwidth=8 --intel 
+#-o "Test.hex"  "Test.out" 
+
+
+
+#================================================
+# Main part of the Makefile starts here. Usually no changes are needed.
+
+# Append U(G Library
+SRC = main.c system_pre_init.c
+SRC += $(shell ls $(U8GDIR)*.c)
+SRC += $(shell ls $(FONTDIR)*.c)
+
+# Internal Variable Names
+LIBNAME:=$(TARGETNAME).a
+ELFNAME:=$(TARGETNAME).elf
+HEXNAME:=$(TARGETNAME).hex
+OBJS := $(SRC:.c=.obj)
+plat_objs = $(addprefix Build/,$(OBJS))
+# TI Compiler
+CC = $(TOOLSPATH)/bin/cl430
+# C flags
+COMMON_FLAGS = --define=F_CPU=$(F_CPU) --define=$(DMCU)
+COMMON_FLAGS += -g
+COMMON_FLAGS += -i"$(U8GDIR)" -i"$(TIPATH)/ccs_base/msp430/include" -i"$(TOOLSPATH)/include"
+COMMON_FLAGS += -vmspx --abi=eabi --data_model=restricted
+COMMON_FLAGS += --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40
+COMMON_FLAGS += --preproc_with_compile
+CFLAGS = $(COMMON_FLAGS)
+# Linker script
+LD_FLAGS = -i"$(TOOLSPATH)/lib" -i"$(MSP4305XXLIB)" -z -m"Test.map" --heap_size=160 --stack_size=160 --use_hw_mpy=F5 --cinit_hold_wdt=on "$(TIPATH)/ccs_base/msp430/include/lnk_msp430f5529.cmd" --rom_model
+
+# Additional Suffixes
+.SUFFIXES: .elf .hex
+
+# Targets
+.PHONY: all
+all: $(ELFNAME) $(HEXNAME)
+
+.PHONY: clean
+clean:
+	$(RM) $(ELFNAME) $(OBJS)
+
+# this is from : https://pythonhosted.org/python-msp430-tools/index.html
+.PHONY: upload
+upload: $(HEXNAME)
+	python -m msp430.bsl5.hid -e $(HEXNAME)
+
+# implicit rules
+.elf.hex:
+	$(MSP430HEX)  $< -o $@
+
+# ti special
+%obj: %c
+	$(CC) $(CFLAGS) -c $< --output_file $@
+
+# explicit rules : linking all .obj files from working dir
+$(ELFNAME): $(OBJS)
+	$(CC) $(COMMON_FLAGS) $(OBJS) $(LD_FLAGS) -o $@

sys/msp430/chess/main.c

@@ -50,6 +50,7 @@ void sys_init(void)
   UCSCTL2 = FLLD_1 + 488;                   // Set DCO Multiplier for 16MHz
   __bic_SR_register(SCG0);                  // Enable the FLL control loop
   __delay_cycles(250000);
+  P3SEL |= BIT0|BIT2;                       // setup alternative mode
 }
 
 int main(void)

sys/msp430/graphics_test/.ccsproject

@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<?ccsproject version="1.0"?>
+<projectOptions>
+	<deviceVariant value="MSP430F5529"/>
+	<deviceFamily value="MSP430"/>
+	<codegenToolVersion value="4.3.3"/>
+	<isElfFormat value="true"/>
+	<connection value="common/targetdb/connections/TIMSP430-USB.xml"/>
+	<linkerCommandFile value="lnk_msp430f5529.cmd"/>
+	<rts value="libc.a"/>
+	<createSlaveProjects value=""/>
+	<templateProperties value="id=com.ti.common.project.core.emptyProjectTemplate,"/>
+	<isTargetManual value="false"/>
+</projectOptions>