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Vivado: Be more concise and helpful in outputs
Don't run Vivado in "tracing mode", which is similar to "set -x" in bash: it dumps all parts of the script, including non-executed lines. This behavior is especially confusing if Vivado dumps code which says "ERROR: ...", but then this code is actually never executed. In non-tracing mode, this source of confusion is removed. As second enhancement, check if the implementation step succeeded before telling users about it. The rather ugly comparison to "100%" is what Xilinx proposes to use in their TCL reference guide, section wait_on_run. For an arbitrary example (with a hook that fails implementation), you get the following behavior before and after this change. Before: ``` source /your/folder/build/toplevel/synth-vivado/vivado_hook_opt_design_post.tcl INFO: [Designcheck 1-1] Checking if ROM memory is mapped to BRAM memory. WARNING: [Vivado 12-180] No cells matched 'get_cells -hierarchical -filter { NAME =~ "*rom_rom*dout_o_reg_2" && PRIMITIVE_TYPE =~ BMEM.*.* }'. ERROR: [Designcheck 1-2] BRAM implementation not found for ROM memory. ERROR: [runtcl-1] ERROR: [Common 17-39] 'send_msg_id' failed due to earlier errors. ERROR: [Common 17-39] 'send_msg_id' failed due to earlier errors. INFO: [Common 17-206] Exiting Vivado at Thu Oct 31 11:26:19 2019... [Thu Oct 31 11:26:19 2019] impl_1 finished wait_on_run: Time (s): cpu = 00:05:40 ; elapsed = 00:06:08 . Memory (MB): peak = 1351.699 ; gain = 0.000 ; free physical = 8259 ; free virtual = 31743 ERROR: Implementation and bitstream generation step failed. while executing "error "ERROR: Implementation and bitstream generation step failed."" invoked from within "if { [get_property PROGRESS [get_runs impl_1]] != "100%"} { error "ERROR: Implementation and bitstream generation step failed." }" (file "toplevel_run.tcl" line 4) INFO: [Common 17-206] Exiting Vivado at Thu Oct 31 11:26:19 2019... make: *** [Makefile:8: toplevel.bit] Fehler 1 ``` After: ``` source /your/folder/build/toplevel/synth-vivado/vivado_hook_opt_design_post.tcl INFO: [Designcheck 1-1] Checking if ROM memory is mapped to BRAM memory. WARNING: [Vivado 12-180] No cells matched 'get_cells -hierarchical -filter { NAME =~ "*rom_rom*dout_o_reg_2" && PRIMITIVE_TYPE =~ BMEM.*.* }'. ERROR: [Designcheck 1-2] BRAM implementation not found for ROM memory. ERROR: [runtcl-1] ERROR: [Common 17-39] 'send_msg_id' failed due to earlier errors. ERROR: [Common 17-39] 'send_msg_id' failed due to earlier errors. INFO: [Common 17-206] Exiting Vivado at Thu Oct 31 11:43:41 2019... [Thu Oct 31 11:43:41 2019] impl_1 finished wait_on_run: Time (s): cpu = 00:05:04 ; elapsed = 00:05:40 . Memory (MB): peak = 1351.699 ; gain = 0.000 ; free physical = 7151 ; free virtual = 31011 ERROR: Implementation and bitstream generation step failed. INFO: [Common 17-206] Exiting Vivado at Thu Oct 31 11:43:41 2019... make: *** [Makefile:8: toplevel.bit] Fehler 1 ```
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