Adding de1 soc rev f

README.md

@@ -144,6 +144,12 @@ FPGA Pin D11 (Connector JP1, pin 38) is used for UART output with 57600 baud rat
 
     fusesoc run --target=de0_nano servant
 
+### DE1 SoC revF
+
+FPGA PIN_AC18 (Connector GPIO0, pin 0) is used for UART output with 57600 baud rate. DE1 SoC revF needs an external 3.3V UART to connect to this pin. The UART pin has not been tested.
+
+    fusesoc run --target=de1_soc_revF servant
+
 ### DECA development kit
 
 FPGA Pin W18 (Pin 3 P8 connector)  is used for UART output with 57600 baud rate. Key 0 is reset and Led 0 q output.

data/de1_soc_revF.sdc

@@ -0,0 +1,8 @@
+# Main system clock (50 Mhz)
+create_clock -name "clk" -period 20.000ns [get_ports {i_clk}]
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty

data/de1_soc_revF.tcl

@@ -0,0 +1,11 @@
+set_location_assignment PIN_AF14 -to i_clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_clk
+
+set_location_assignment PIN_AA14 -to i_rst_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_rst_n
+
+set_location_assignment PIN_V16 -to q
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to q
+
+set_location_assignment PIN_AC18 -to uart_txd
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart*

servant.core

@@ -69,6 +69,13 @@ filesets:
       - servant/servive_clock_gen.v : {file_type : verilogSource}
       - servant/servive.v : {file_type : verilogSource}
 
+  de1_soc_revF:
+    files:
+      - data/de1_soc_revF.sdc : {file_type : SDC}
+      - data/de1_soc_revF.tcl : {file_type : tclSource}
+      - servant/servde1_soc_revF_clock_gen.v : {file_type : verilogSource}
+      - servant/servde1_soc_revF.v : {file_type : verilogSource}
+
   tinyfpga_bx: {files: [data/tinyfpga_bx.pcf : {file_type : PCF}]}
   icebreaker : {files: [data/icebreaker.pcf  : {file_type : PCF}]}
   icesugar   : {files: [data/icesugar.pcf : {file_type : PCF}]}
@@ -181,6 +188,17 @@ targets:
         device : EP4CE22F17C6
     toplevel: servive
 
+  de1_soc_revF:
+    default_tool : quartus
+    filesets : [mem_files, soc, de1_soc_revF]
+    parameters : [memfile, memsize]
+    tools:
+      quartus:
+        family : Cyclone V
+        device : 5CSEMA5F31C6
+        board_device_index : 2
+    toplevel: servde1_soc_revF
+
   icebreaker:
     default_tool : icestorm
     filesets : [mem_files, soc, service, icebreaker]

servant/servde1_soc_revF.v

@@ -0,0 +1,31 @@
+`default_nettype none
+module servde1_soc_revF
+(
+ input wire 	   i_clk,
+ input wire 	   i_rst_n,
+ output wire 	   q,
+ output wire 	   uart_txd);
+
+   parameter memfile = "zephyr_hello.hex";
+   parameter memsize = 8192;
+
+   wire      wb_clk;
+   wire      wb_rst;
+
+   assign uart_txd = q;
+
+   servde1_soc_revF_clock_gen clock_gen
+     (.i_clk (i_clk),
+      .i_rst (!i_rst_n),
+      .o_clk (wb_clk),
+      .o_rst (wb_rst));
+
+   servant
+     #(.memfile (memfile),
+       .memsize (memsize))
+   servant
+     (.wb_clk (wb_clk),
+      .wb_rst (wb_rst),
+      .q      (q));
+
+endmodule

servant/servde1_soc_revF_clock_gen.v

@@ -0,0 +1,34 @@
+`default_nettype none
+module servde1_soc_revF_clock_gen
+  (input wire i_clk,
+   input wire i_rst,
+   output wire o_clk,
+   output wire o_rst);
+
+   wire        locked;
+   reg [9:0]   r;
+
+   assign o_rst = r[9];
+
+   always @(posedge o_clk)
+     if (locked)
+       r <= {r[8:0],1'b0};
+     else
+       r <= 10'b1111111111;
+
+   wire [5:0] 	  clk;
+
+   assign 	  o_clk = clk[0];
+
+   altpll
+     #(.operation_mode         ("NORMAL"),
+       .clk0_divide_by         (25),
+       .clk0_multiply_by       (8),
+       .inclk0_input_frequency (20000))
+   pll
+     (.areset       (i_rst),
+      .inclk        ({1'b0, i_clk}),
+      .clk          (clk),
+      .locked       (locked));
+
+endmodule