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Fix odt RD/WR fields
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Change-Id: I4aaa23af53a72e4f90218daedbed80d8721ff337
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/86280
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/86542
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
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@markypizz @dcrowell77
markypizz authored and dcrowell77 committed Nov 13, 2019
1 parent fcbb094 commit 3f280b8
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Showing 6 changed files with 170 additions and 34 deletions.
72 changes: 67 additions & 5 deletions src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H
View file
Original file line number Diff line number Diff line change
Expand Up @@ -154,7 +154,10 @@ enum msdg_enable
///
enum odt_fields
{
FLD_LENGTH = 4,
R2_FLD_LENGTH = 2, // R2 = 2 rank (normal / 2 rank mode: makes use of 2 bits)
R4_FLD_LENGTH = 4, // R4 = 4 rank (4 rank mode: makes use of 4 bits)
ODT_MIDPOINT = 4,
R4_SHIFT = 2,
RANK3 = 12,
RANK2 = 8,
RANK1 = 4,
Expand Down Expand Up @@ -527,6 +530,9 @@ class phy_params
fapi2::ReturnCode populate_odt_buffer(const uint8_t (&i_odt_rd_wr_attr)[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM],
fapi2::buffer<uint16_t>& o_odt_buffer) const
{
// TK - Update code for encoded quad CS, waiting on SPD
// static constexpr bool ENCODED_QUAD_CS_ENABLE = true;

// Const vector to map phy ranks to their buffer offset position
const std::vector<uint8_t> l_buffer_rank_offset =
{
Expand All @@ -538,10 +544,66 @@ class phy_params

for (const auto& l_rank : iv_rank_info)
{
const auto OFFSET = l_buffer_rank_offset[l_rank.get_phy_rank()];
const auto DIMM_RANK = l_rank.get_dimm_rank();
const auto DIMM_INDEX = mss::index(l_rank.get_dimm_target());
FAPI_TRY(o_odt_buffer.insert(i_odt_rd_wr_attr[DIMM_INDEX][DIMM_RANK], OFFSET, odt_fields::FLD_LENGTH));
if (iv_params.iv_rank4_mode[0] == fapi2::ENUM_ATTR_MEM_EFF_FOUR_RANK_MODE_ENABLE)
{
// A & B separate. We need to do a bit if shifting from our attribute
// our attribute is aligned XX00YY00 but we want XXYY0000
// The attr must be populated this way, as we only have 4 ODTs and they are aligned as such
// Otherwise, we have problems on the SPD/decoder side
// where XX is A0A1 (bits 0,1) and YY is B0B1 (bits 4,5)

// From MCHP spec:
// OdtRdMapCs BIT [1:0] ODT_A[1:0] value when reading to rank 0
// OdtRdMapCs BIT [3:2] ODT_B[1:0] value when reading to rank 0
// ...

const auto OFFSET = l_buffer_rank_offset[l_rank.get_phy_rank()];
const auto DIMM_RANK = l_rank.get_dimm_rank();
const auto DIMM_INDEX = mss::index(l_rank.get_dimm_target());

uint8_t l_data = 0;

// l_data populated as such:
// XX000000 || 0000YY00 << 2
l_data = i_odt_rd_wr_attr[DIMM_INDEX][DIMM_RANK];
l_data |= (i_odt_rd_wr_attr[DIMM_INDEX][DIMM_RANK] << odt_fields::R4_SHIFT);

// Sanity check: bitwise and the relevant bits
l_data &= 0b11110000;

// Now we have XXYY0000
// Insert into the buffer
FAPI_TRY(o_odt_buffer.insert(l_data, OFFSET, odt_fields::R4_FLD_LENGTH));
}
// TK: need more information for encoded_quadcs (4U only)
// else if (iv_params.iv_encoded_quadcs == ENCODED_QUAD_CS_ENABLE)
// {
// }
else
{
// For DDIMM:
// A & B together. B0 (ODT2) mirrors A0 (ODT0), B1 (ODT3) mirrors A1 (ODT1)
// ODTA/B [1:0] == [ODT3/1:ODT2/0]

// From MCHP spec:
// OdtRdMapCs BIT [1:0] ODTA/B[1:0] value when reading to rank 0
// So it already accounts for any mirroring, we just need to plop in the value

const auto OFFSET = l_buffer_rank_offset[l_rank.get_phy_rank()];
const auto DIMM_RANK = l_rank.get_dimm_rank();
const auto DIMM_INDEX = mss::index(l_rank.get_dimm_target());

uint8_t l_data = 0;
l_data = i_odt_rd_wr_attr[DIMM_INDEX][DIMM_RANK];

// Finally, put it back

// Insert l_data (attribute) from the corresponding dimm's position:
// DIMM0 (ODT0, ODT1) (bits 0,1) or DIMM1 ODT0, ODT1 (bits 4,5) (though DIMM1 probably wouldn't be applicable here)
// at the offset to match the draminit field.
//
FAPI_TRY(o_odt_buffer.insert(l_data, OFFSET, odt_fields::R2_FLD_LENGTH, DIMM_INDEX * odt_fields::ODT_MIDPOINT));
}
}

// Rest of the buffer should already be zeroed from declaration
Expand Down
38 changes: 30 additions & 8 deletions src/import/chips/ocmb/procedures/hwp/initfiles/explorer_scom.C
View file
Original file line number Diff line number Diff line change
Expand Up @@ -198,6 +198,12 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP
l_def_SLOT1_DENOMINATOR);
fapi2::ATTR_MEM_SI_ODT_RD_Type l_TGT1_ATTR_MEM_SI_ODT_RD;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_ODT_RD, TGT1, l_TGT1_ATTR_MEM_SI_ODT_RD));
uint64_t l_def_dual_drop = ((l_TGT1_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM[literal_0] > literal_0)
&& (l_TGT1_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM[literal_1] > literal_0));
fapi2::ATTR_MEM_EFF_FOUR_RANK_MODE_Type l_TGT1_ATTR_MEM_EFF_FOUR_RANK_MODE;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_FOUR_RANK_MODE, TGT1, l_TGT1_ATTR_MEM_EFF_FOUR_RANK_MODE));
uint64_t l_def_four_rank_mode = (l_TGT1_ATTR_MEM_EFF_FOUR_RANK_MODE[literal_0] == literal_1);
uint64_t l_def_cs_tied = ((l_def_four_rank_mode == literal_0) && (l_def_dual_drop == literal_0));
fapi2::ATTR_MEM_SI_ODT_WR_Type l_TGT1_ATTR_MEM_SI_ODT_WR;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_ODT_WR, TGT1, l_TGT1_ATTR_MEM_SI_ODT_WR));
uint64_t l_def_NUM_RANKS = (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] +
Expand Down Expand Up @@ -629,12 +635,20 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP

l_scom_buffer.insert<0, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_0] >> literal_7) );
l_scom_buffer.insert<1, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_0] >> literal_6) );
l_scom_buffer.insert<2, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_0] >> literal_3) );
l_scom_buffer.insert<3, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_0] >> literal_2) );
l_scom_buffer.insert<2, 1, 63, uint64_t>(((((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_0] >> literal_3) &
literal_0b1) && (l_def_cs_tied == literal_0))
|| (((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_0] >> literal_7) & literal_0b1) && (l_def_cs_tied == literal_1))) );
l_scom_buffer.insert<3, 1, 63, uint64_t>(((((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_0] >> literal_2) &
literal_0b1) && (l_def_cs_tied == literal_0))
|| (((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_0] >> literal_6) & literal_0b1) && (l_def_cs_tied == literal_1))) );
l_scom_buffer.insert<4, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_1] >> literal_7) );
l_scom_buffer.insert<5, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_1] >> literal_6) );
l_scom_buffer.insert<6, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_1] >> literal_3) );
l_scom_buffer.insert<7, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_1] >> literal_2) );
l_scom_buffer.insert<6, 1, 63, uint64_t>(((((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_1] >> literal_3) &
literal_0b1) && (l_def_cs_tied == literal_0))
|| (((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_1] >> literal_7) & literal_0b1) && (l_def_cs_tied == literal_1))) );
l_scom_buffer.insert<7, 1, 63, uint64_t>(((((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_1] >> literal_2) &
literal_0b1) && (l_def_cs_tied == literal_0))
|| (((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_1] >> literal_6) & literal_0b1) && (l_def_cs_tied == literal_1))) );
l_scom_buffer.insert<8, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_2] >> literal_7) );
l_scom_buffer.insert<9, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_2] >> literal_6) );
l_scom_buffer.insert<10, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_2] >> literal_3) );
Expand All @@ -661,12 +675,20 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP
l_scom_buffer.insert<31, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_1][literal_3] >> literal_2) );
l_scom_buffer.insert<32, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_0] >> literal_7) );
l_scom_buffer.insert<33, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_0] >> literal_6) );
l_scom_buffer.insert<34, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_0] >> literal_3) );
l_scom_buffer.insert<35, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_0] >> literal_2) );
l_scom_buffer.insert<34, 1, 63, uint64_t>(((((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_0] >> literal_3) &
literal_0b1) && (l_def_cs_tied == literal_0))
|| (((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_0] >> literal_7) & literal_0b1) && (l_def_cs_tied == literal_1))) );
l_scom_buffer.insert<35, 1, 63, uint64_t>(((((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_0] >> literal_2) &
literal_0b1) && (l_def_cs_tied == literal_0))
|| (((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_0] >> literal_6) & literal_0b1) && (l_def_cs_tied == literal_1))) );
l_scom_buffer.insert<36, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_1] >> literal_7) );
l_scom_buffer.insert<37, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_1] >> literal_6) );
l_scom_buffer.insert<38, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_1] >> literal_3) );
l_scom_buffer.insert<39, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_1] >> literal_2) );
l_scom_buffer.insert<38, 1, 63, uint64_t>(((((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_1] >> literal_3) &
literal_0b1) && (l_def_cs_tied == literal_0))
|| (((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_1] >> literal_7) & literal_0b1) && (l_def_cs_tied == literal_1))) );
l_scom_buffer.insert<39, 1, 63, uint64_t>(((((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_1] >> literal_2) &
literal_0b1) && (l_def_cs_tied == literal_0))
|| (((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_1] >> literal_6) & literal_0b1) && (l_def_cs_tied == literal_1))) );
l_scom_buffer.insert<40, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_2] >> literal_7) );
l_scom_buffer.insert<41, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_2] >> literal_6) );
l_scom_buffer.insert<42, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_2] >> literal_3) );
Expand Down
46 changes: 29 additions & 17 deletions src/import/generic/memory/lib/data_engine/attr_engine_traits.H
View file
Original file line number Diff line number Diff line change
Expand Up @@ -40,11 +40,11 @@
#include <generic/memory/lib/spd/spd_facade.H>
#include <generic/memory/lib/data_engine/data_engine_traits_def.H>
#include <generic/memory/lib/data_engine/data_engine.H>
#include <generic/memory/lib/data_engine/data_engine_utils.H>
#include <generic/memory/lib/mss_generic_attribute_getters.H>
#include <generic/memory/lib/mss_generic_attribute_setters.H>
#include <generic/memory/lib/mss_generic_system_attribute_getters.H>
#include <generic/memory/lib/spd/ddimm/efd_decoder.H>
#include <generic/memory/lib/utils/buffer_ops.H>
#include <generic/memory/lib/utils/dimm/mss_timing.H>
#include <generic/memory/lib/spd/spd_utils.H>

Expand Down Expand Up @@ -1831,6 +1831,8 @@ struct attrEngineTraits<P, attr_si_engine_fields, attr_si_engine_fields::SI_ODT_
{
uint8_t l_value = 0;

const auto l_ocmb = i_efd_data->get_ocmb_target();

switch(i_efd_data->get_rank())
{
case 0:
Expand All @@ -1850,17 +1852,21 @@ struct attrEngineTraits<P, attr_si_engine_fields, attr_si_engine_fields::SI_ODT_
break;

default:
// TODO Add FFDC
fapi2::Assert(false);
FAPI_ASSERT(false,
fapi2::MSS_INVALID_SPD_RANK().
set_FUNCTION(SET_SI_ODT_WR).
set_RANK( i_efd_data->get_rank() ).
set_TARGET(l_ocmb),
"%s SPD decoder returned invalid rank: %d",
spd::c_str(l_ocmb),
i_efd_data->get_rank());
break;
};

// TK update to handle differentiating 2 DIMMs, defaulted to DIMM0 case for explorer
{
// Map to attribute bitmap
reverse(l_value);
o_setting = l_value;
}
// Map to attribute bitmap
l_value = mss::gen::align_odt_field_to_attr(l_value);

o_setting = l_value;

fapi_try_exit:
return fapi2::current_err;
Expand Down Expand Up @@ -1916,6 +1922,8 @@ struct attrEngineTraits<P, attr_si_engine_fields, attr_si_engine_fields::SI_ODT_
{
uint8_t l_value = 0;

const auto l_ocmb = i_efd_data->get_ocmb_target();

switch(i_efd_data->get_rank())
{
case 0:
Expand All @@ -1935,17 +1943,21 @@ struct attrEngineTraits<P, attr_si_engine_fields, attr_si_engine_fields::SI_ODT_
break;

default:
// TODO Add FFDC
fapi2::Assert(false);
FAPI_ASSERT(false,
fapi2::MSS_INVALID_SPD_RANK().
set_FUNCTION(SET_SI_ODT_RD).
set_RANK( i_efd_data->get_rank() ).
set_TARGET(l_ocmb),
"%s SPD decoder returned invalid rank: %d",
spd::c_str(l_ocmb),
i_efd_data->get_rank());
break;
};

// TK update to handle differentiating 2 DIMMs, defaulted to DIMM0 case for explorer
{
// Map to attribute bitmap
reverse(l_value);
o_setting = l_value;
}
// Map to attribute bitmap
l_value = mss::gen::align_odt_field_to_attr(l_value);

o_setting = l_value;

fapi_try_exit:
return fapi2::current_err;
Expand Down
34 changes: 34 additions & 0 deletions src/import/generic/memory/lib/data_engine/data_engine_utils.H
View file
Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,7 @@
#include <generic/memory/lib/mss_generic_attribute_getters.H>
#include <generic/memory/lib/utils/conversions.H>
#include <generic/memory/lib/utils/shared/mss_generic_consts.H>
#include <generic/memory/lib/utils/buffer_ops.H>

namespace mss
{
Expand Down Expand Up @@ -478,6 +479,39 @@ fapi_try_exit:
return fapi2::current_err;
}

///
/// @brief Shift the bits of the SPD field to match the attribute format
/// @param[in] i_value ODT field value from SPD
/// @return ATTR formatted uint8_t
///
static inline uint8_t align_odt_field_to_attr(const uint8_t i_value)
{
static constexpr uint8_t ODT2_OLD = 2;
static constexpr uint8_t ODT3_OLD = 3;
static constexpr uint8_t ODT2 = 4;
static constexpr uint8_t ODT3 = 5;

fapi2::buffer<uint8_t> l_value(i_value);
// Map to attribute bitmap
reverse(l_value);

// l_value currently looks like:
// XXYY0000
// ODT
// 0123----
//
// We need it to look like:
// XX00YY00
// 01--23--
l_value.writeBit<ODT2>(l_value.getBit<ODT2_OLD>());
l_value.writeBit<ODT3>(l_value.getBit<ODT3_OLD>());

l_value.clearBit<ODT2_OLD>();
l_value.clearBit<ODT3_OLD>();

return l_value();
}

}// gen
}//mss

Expand Down
12 changes: 8 additions & 4 deletions src/import/generic/memory/lib/mss_generic_attribute_getters.H
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4190,7 +4190,8 @@ fapi_try_exit:
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note Array[DIMM][RANK] READ, On Die Termination triggering bitmap. Use bitmap to determine
/// which ODT to fire for the designated rank. The bits in 8 bit field are [DIMM0 ODT0][DIMM0
/// ODT1][DIMM0 ODT2][DIMM0 ODT3][DIMM1 ODT0][DIMM1 ODT1][DIMM1 ODT2][DIMM1 ODT3]
/// ODT1][DIMM0 ODT2][DIMM0 ODT3][DIMM1 ODT0][DIMM1 ODT1][DIMM1 ODT2][DIMM1 ODT3] For
/// Explorer: Only bits 0,1,4,5 are used. They correspond to A0 A1 -- -- B0 B1 -- --
///
inline fapi2::ReturnCode get_si_odt_rd(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t (&o_array)[4])
{
Expand All @@ -4215,7 +4216,8 @@ fapi_try_exit:
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note Array[DIMM][RANK] READ, On Die Termination triggering bitmap. Use bitmap to determine
/// which ODT to fire for the designated rank. The bits in 8 bit field are [DIMM0 ODT0][DIMM0
/// ODT1][DIMM0 ODT2][DIMM0 ODT3][DIMM1 ODT0][DIMM1 ODT1][DIMM1 ODT2][DIMM1 ODT3]
/// ODT1][DIMM0 ODT2][DIMM0 ODT3][DIMM1 ODT0][DIMM1 ODT1][DIMM1 ODT2][DIMM1 ODT3] For
/// Explorer: Only bits 0,1,4,5 are used. They correspond to A0 A1 -- -- B0 B1 -- --
///
inline fapi2::ReturnCode get_si_odt_rd(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
uint8_t (&o_array)[2][4])
Expand All @@ -4240,7 +4242,8 @@ fapi_try_exit:
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note Array[DIMM][RANK] WRITE, On Die Termination triggering bitmap. Use bitmap to determine
/// which ODT to fire for the designated rank. The bits in 8 bit field are [DIMM0 ODT0][DIMM0
/// ODT1][DIMM0 ODT2][DIMM0 ODT3][DIMM1 ODT0][DIMM1 ODT1][DIMM1 ODT2][DIMM1 ODT3]
/// ODT1][DIMM0 ODT2][DIMM0 ODT3][DIMM1 ODT0][DIMM1 ODT1][DIMM1 ODT2][DIMM1 ODT3] For
/// Explorer: Only bits 0,1,4,5 are used. They correspond to A0 A1 -- -- B0 B1 -- --
///
inline fapi2::ReturnCode get_si_odt_wr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t (&o_array)[4])
{
Expand All @@ -4265,7 +4268,8 @@ fapi_try_exit:
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note Array[DIMM][RANK] WRITE, On Die Termination triggering bitmap. Use bitmap to determine
/// which ODT to fire for the designated rank. The bits in 8 bit field are [DIMM0 ODT0][DIMM0
/// ODT1][DIMM0 ODT2][DIMM0 ODT3][DIMM1 ODT0][DIMM1 ODT1][DIMM1 ODT2][DIMM1 ODT3]
/// ODT1][DIMM0 ODT2][DIMM0 ODT3][DIMM1 ODT0][DIMM1 ODT1][DIMM1 ODT2][DIMM1 ODT3] For
/// Explorer: Only bits 0,1,4,5 are used. They correspond to A0 A1 -- -- B0 B1 -- --
///
inline fapi2::ReturnCode get_si_odt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target,
uint8_t (&o_array)[2][4])
Expand Down
2 changes: 2 additions & 0 deletions src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -458,6 +458,7 @@
READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank.
The bits in 8 bit field are
[DIMM0 ODT0][DIMM0 ODT1][DIMM0 ODT2][DIMM0 ODT3][DIMM1 ODT0][DIMM1 ODT1][DIMM1 ODT2][DIMM1 ODT3]
For Explorer: Only bits 0,1,4,5 are used. They correspond to A0 A1 -- -- B0 B1 -- --
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
Expand All @@ -474,6 +475,7 @@
WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank.
The bits in 8 bit field are
[DIMM0 ODT0][DIMM0 ODT1][DIMM0 ODT2][DIMM0 ODT3][DIMM1 ODT0][DIMM1 ODT1][DIMM1 ODT2][DIMM1 ODT3]
For Explorer: Only bits 0,1,4,5 are used. They correspond to A0 A1 -- -- B0 B1 -- --
</description>
<initToZero></initToZero>
<valueType>uint8</valueType>
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