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L3 Update - p9_phb_hv_utils HWP
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Change-Id: If1e832307cbb57924be8ef7aaa981a44fb32de2d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43160
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48379
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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@ibmthi @dcrowell77
ibmthi authored and dcrowell77 committed Oct 16, 2017
1 parent bd05ce5 commit 4b4eded
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292 changes: 141 additions & 151 deletions src/import/chips/p9/procedures/hwp/nest/p9_phb_hv_utils.C
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Expand Up @@ -22,192 +22,182 @@
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
//-----------------------------------------------------------------------------------
//
//

///---------------------------------------------------------------------------
///
/// @file p9_phb_hv_utils.C
/// @brief Functions to access PHB HV register space (FAPI)
/// @brief Functions to access PHB HV register space (FAPI2)
///
// *HWP HWP Owner: Ricardo Mata Jr. ricmata@us.ibm.com
// *HWP FW Owner: Thi Tran thi@us.ibm.com
// *HWP Team: Nest
// *HWP Level: 2
// *HWP Consumed by: HB
//
//-----------------------------------------------------------------------------------


//-----------------------------------------------------------------------------------
// Includes
//-----------------------------------------------------------------------------------
#include <p9_phb_hv_utils.H>
#include "p9_misc_scom_addresses.H"
#include "p9_misc_scom_addresses_fld.H"
/// *HWP HWP Owner: Ricardo Mata Jr. ricmata@us.ibm.com
/// *HWP FW Owner: Thi Tran thi@us.ibm.com
/// *HWP Team: Nest
/// *HWP Level: 3
/// *HWP Consumed by: FSP
///
///---------------------------------------------------------------------------

extern "C"
{
///---------------------------------------------------------------------------
/// Includes
///---------------------------------------------------------------------------
#include <p9_phb_hv_utils.H>
#include <p9_misc_scom_addresses.H>
#include <p9_misc_scom_addresses_fld.H>

//---------------------------------------------------------------------------------
// NOTE: description in header
//---------------------------------------------------------------------------------
fapi2::ReturnCode p9_phb_hv_check_etu_state(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target)
{
FAPI_DBG(" Start p9_phb_hv_check_etu_state");

fapi2::buffer<uint64_t> l_buf;

//Read state of ETU Reset Register
FAPI_TRY(fapi2::getScom(i_target, PHB_PHBRESET_REG, l_buf));
FAPI_DBG(" ETU Reset Register %#lx", l_buf());

FAPI_ASSERT(!l_buf.getBit<PHB_PHBRESET_REG_PE_ETU_RESET>(),
fapi2::P9_PHB_HV_UTILS_ETU_RESET_ACTIVE()
.set_TARGET(i_target)
.set_ADDRESS(PHB_PHBRESET_REG)
.set_DATA(l_buf),
" ETU is in reset!");


fapi_try_exit:
FAPI_DBG(" Exiting p9_phb_hv_check_etu_state");
return fapi2::current_err;
}

fapi2::ReturnCode p9_phb_hv_check_etu_state(
const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target)
{
FAPI_DBG(" Start p9_phb_hv_check_etu_state");
fapi2::buffer<uint64_t> l_buf;

//Read state of ETU Reset Register
FAPI_TRY(fapi2::getScom(i_target, PHB_PHBRESET_REG, l_buf),
"Error from getScom (0x%.16llX)", PHB_PHBRESET_REG);
FAPI_DBG(" ETU Reset Register %#lx", l_buf());
FAPI_ASSERT(!l_buf.getBit<PHB_PHBRESET_REG_PE_ETU_RESET>(),
fapi2::P9_PHB_HV_UTILS_ETU_RESET_ACTIVE()
.set_TARGET(i_target)
.set_ADDRESS(PHB_PHBRESET_REG)
.set_DATA(l_buf),
" ETU is in reset!");

fapi_try_exit:
FAPI_DBG(" Exiting p9_phb_hv_check_etu_state");
return fapi2::current_err;
}

//---------------------------------------------------------------------------------
// NOTE: description in header
//---------------------------------------------------------------------------------
fapi2::ReturnCode p9_phb_hv_check_args(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, const uint32_t i_address,
bool const i_size)
fapi2::ReturnCode p9_phb_hv_check_args(
const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target,
const uint32_t i_address,
bool const i_size)
{
FAPI_DBG(" Start p9_phb_hv_check_args");
uint32_t l_actualTransSize;

if (i_size)
{
FAPI_DBG(" Start p9_phb_hv_check_args");

uint32_t l_actualTransSize;

if (i_size)
{
l_actualTransSize = 4;
}
else
{
l_actualTransSize = 8;
}

FAPI_DBG(" Addr 0x%04llX, Size 0x%d", i_address, l_actualTransSize);

//Check the address alignment
FAPI_ASSERT(!(i_address & (l_actualTransSize - 1)),
fapi2::P9_PHB_HV_UTILS_INVALID_ARGS()
.set_TARGET(i_target)
.set_ADDRESS(i_address),
" Address is not aligned");

//Make sure the address is within the PHB HV bounds
FAPI_ASSERT(i_address <= PHB_HV_MAX_ADDR,
fapi2::P9_PHB_HV_UTILS_INVALID_ARGS()
.set_TARGET(i_target)
.set_ADDRESS(i_address),
" Address exceeds supported PHB HV address range, 0x0000 - 0x1FFF");


fapi_try_exit:
FAPI_DBG(" Exiting p9_phb_hv_check_args");
return fapi2::current_err;
l_actualTransSize = 4;
}
else
{
l_actualTransSize = 8;
}

FAPI_DBG(" Addr 0x%04llX, Size 0x%d", i_address, l_actualTransSize);

//Check the address alignment
FAPI_ASSERT(!(i_address & (l_actualTransSize - 1)),
fapi2::P9_PHB_HV_UTILS_INVALID_ARGS()
.set_TARGET(i_target)
.set_ADDRESS(i_address)
.set_SIZE(l_actualTransSize),
"Input address (0x%04llX) is not aligned", i_address);

//Make sure the address is within the PHB HV bounds
FAPI_ASSERT(i_address <= PHB_HV_MAX_ADDR,
fapi2::P9_PHB_HV_UTILS_INVALID_ARGS()
.set_TARGET(i_target)
.set_ADDRESS(i_address)
.set_SIZE(l_actualTransSize),
"Input addr (0x%04llX) exceeds supported PHB HV address of "
"0x%04llX", i_address, PHB_HV_MAX_ADDR);

fapi_try_exit:
FAPI_DBG(" Exiting p9_phb_hv_check_args");
return fapi2::current_err;
}

//---------------------------------------------------------------------------------
// NOTE: description in header
//---------------------------------------------------------------------------------
fapi2::ReturnCode p9_phb_hv_setup(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, const uint32_t i_address,
bool const i_size)
{
FAPI_DBG(" Start p9_phb_hv_setup");

fapi2::buffer<uint64_t> phb_hv_addr_reg_data(i_address);

//Set Valid bit to allow read/write access
phb_hv_addr_reg_data.setBit<PHB_HV_IND_ADDR_VALID_BIT>();

//Set Size for 8B or 4B ops
if (i_size)
{
phb_hv_addr_reg_data.setBit<PHB_HV_IND_ADDR_SIZE_BIT>();
}

fapi2::ReturnCode p9_phb_hv_setup(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, const uint32_t i_address,
bool const i_size)
{
FAPI_DBG(" Start p9_phb_hv_setup");
fapi2::buffer<uint64_t> phb_hv_addr_reg_data(i_address);

//This sets everything that should be set for the PHB HV Indirect Address Register
FAPI_DBG(" PHB HV Indirect Address Register 0x%016llX", phb_hv_addr_reg_data);
FAPI_TRY(fapi2::putScom(i_target, PHB_HV_INDIRECT_ADDR_REG, phb_hv_addr_reg_data),
" Error writing to PHB HV Indirect Address Register");
//Set Valid bit to allow read/write access
phb_hv_addr_reg_data.setBit<PHB_PHB4_SCOM_HVIAR_HV_REQ_ADDR_VLD>();

fapi_try_exit:
FAPI_DBG(" Exiting p9_phb_hv_setup");
return fapi2::current_err;
//Set Size for 8B or 4B ops
if (i_size)
{
phb_hv_addr_reg_data.setBit<PHB_PHB4_SCOM_HVIAR_HV_REQ_4B>();
}

//This sets everything that should be set for the PHB HV Indirect Address Register
FAPI_DBG(" PHB HV Indirect Address Register 0x%016llX", phb_hv_addr_reg_data);
FAPI_TRY(fapi2::putScom(i_target, PHB_PHB4_SCOM_HVIAR, phb_hv_addr_reg_data),
"Error from putScom (0x%.16llX)", PHB_PHB4_SCOM_HVIAR);

fapi_try_exit:
FAPI_DBG(" Exiting p9_phb_hv_setup");
return fapi2::current_err;
}

//---------------------------------------------------------------------------------
// NOTE: description in header
//---------------------------------------------------------------------------------
fapi2::ReturnCode p9_phb_hv_write(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, const uint32_t i_address,
bool const i_size, uint64_t& i_write_data)
{
FAPI_DBG(" Start p9_phb_hv_write");

fapi2::buffer<uint64_t> phb_hv_data_reg_data(i_write_data);

//write the data into the PHB HV Indirect Data Register
FAPI_DBG(" Write Data = 0x%016llX", phb_hv_data_reg_data);
FAPI_TRY(fapi2::putScom(i_target, PHB_HV_INDIRECT_DATA_REG, phb_hv_data_reg_data),
" Error writing to PHB HV Indirect Data Register");
fapi2::ReturnCode p9_phb_hv_write(
const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target,
const uint32_t i_address,
bool const i_size, uint64_t& i_write_data)
{
FAPI_DBG(" Start p9_phb_hv_write");
fapi2::buffer<uint64_t> phb_hv_data_reg_data(i_write_data);

//write the data into the PHB HV Indirect Data Register
FAPI_DBG(" Write Data = 0x%016llX", phb_hv_data_reg_data);
FAPI_TRY(fapi2::putScom(i_target, PHB_PHB4_SCOM_HVIDR, phb_hv_data_reg_data),
"Error from putScom (0x%.16llX)", PHB_PHB4_SCOM_HVIDR);

fapi_try_exit:
FAPI_DBG(" Exiting p9_phb_hv_write");
return fapi2::current_err;
}
fapi_try_exit:
FAPI_DBG(" Exiting p9_phb_hv_write");
return fapi2::current_err;
}

//---------------------------------------------------------------------------------
// NOTE: description in header
//---------------------------------------------------------------------------------
fapi2::ReturnCode p9_phb_hv_read(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, const uint32_t i_address,
bool const i_size, uint64_t& o_read_data)
{
FAPI_DBG(" Start p9_phb_hv_read");

fapi2::buffer<uint64_t> phb_hv_data_reg_data;

//Read data from PHB HV Indirect Data Register
FAPI_TRY(fapi2::getScom(i_target, PHB_HV_INDIRECT_DATA_REG, phb_hv_data_reg_data),
" Error writing to PHB HV Indirect Data Register");
o_read_data = phb_hv_data_reg_data;
FAPI_DBG(" Read Data = 0x%016llX", o_read_data);

fapi2::ReturnCode p9_phb_hv_read(
const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target,
const uint32_t i_address,
bool const i_size,
uint64_t& o_read_data)
{
FAPI_DBG(" Start p9_phb_hv_read");
fapi2::buffer<uint64_t> phb_hv_data_reg_data;

fapi_try_exit:
FAPI_DBG(" Exiting p9_phb_hv_read");
return fapi2::current_err;
}
//Read data from PHB HV Indirect Data Register
FAPI_TRY(fapi2::getScom(i_target, PHB_PHB4_SCOM_HVIDR, phb_hv_data_reg_data),
"Error from getScom (0x%.16llX)", PHB_PHB4_SCOM_HVIDR);
o_read_data = phb_hv_data_reg_data;
FAPI_DBG(" Read Data = 0x%016llX", o_read_data);

fapi_try_exit:
FAPI_DBG(" Exiting p9_phb_hv_read");
return fapi2::current_err;
}

//---------------------------------------------------------------------------------
// NOTE: description in header
//---------------------------------------------------------------------------------
fapi2::ReturnCode p9_phb_hv_clear(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target)
{
FAPI_DBG(" Start p9_phb_hv_clear");

fapi2::buffer<uint64_t> phb_hv_addr_reg_data = 0;

//Clear the contents of the PHB HV Indirect Address Register
FAPI_DBG(" PHB HV Indirect Address Register 0x%016llX", phb_hv_addr_reg_data);
FAPI_TRY(fapi2::putScom(i_target, PHB_HV_INDIRECT_ADDR_REG, phb_hv_addr_reg_data),
" Error writing to PHB HV Indirect Address Register");

fapi_try_exit:
FAPI_DBG(" Exiting p9_phb_hv_clear");
return fapi2::current_err;
}

} // extern "C
fapi2::ReturnCode p9_phb_hv_clear(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target)
{
FAPI_DBG(" Start p9_phb_hv_clear");
fapi2::buffer<uint64_t> phb_hv_addr_reg_data = 0;

//Clear the contents of the PHB HV Indirect Address Register
FAPI_DBG(" PHB HV Indirect Address Register 0x%016llX", phb_hv_addr_reg_data);
FAPI_TRY(fapi2::putScom(i_target, PHB_PHB4_SCOM_HVIAR, phb_hv_addr_reg_data),
"Error from putScom (0x%.16llX)", PHB_PHB4_SCOM_HVIAR);

fapi_try_exit:
FAPI_DBG(" Exiting p9_phb_hv_clear");
return fapi2::current_err;
}

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