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DMI Linktraining and Centaur Dccal
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Change-Id: Ib5103f97b30307221d1e2699d1b58315e056615c
Original-Change-Id: I29e43df88a2a4ff2fff0b6bea8d1608a0b78edb1
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41730
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gary A. Peterson <garyp@us.ibm.com>
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45333
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
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@steffenchris @crgeddes
steffenchris authored and crgeddes committed Aug 30, 2017
1 parent e95b05a commit 99ceaa4
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Showing 5 changed files with 842 additions and 532 deletions.
119 changes: 94 additions & 25 deletions src/import/chips/p9/procedures/hwp/io/p9_io_dmi_clear_firs.C
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Original file line number Diff line number Diff line change
Expand Up @@ -54,81 +54,150 @@
//-----------------------------------------------------------------------------
// Definitions
//-----------------------------------------------------------------------------
fapi2::ReturnCode io_rx_fir_reset(
const fapi2::Target < fapi2::TARGET_TYPE_DMI >& i_target);
fapi2::ReturnCode io_dmi_proc_rx_fir_reset(const DMI_PROC_TGT& i_tgt);
fapi2::ReturnCode io_dmi_proc_tx_fir_reset(const DMI_PROC_TGT& i_tgt);

fapi2::ReturnCode io_tx_fir_reset(
const fapi2::Target < fapi2::TARGET_TYPE_DMI >& i_target);
fapi2::ReturnCode io_dmi_cn_rx_fir_reset(const DMI_CN_TGT& i_tgt);
fapi2::ReturnCode io_dmi_cn_tx_fir_reset(const DMI_CN_TGT& i_tgt);

/**
* @brief Clears PHY Rx/Tx FIRs on the DMI(EDI+) specified target. The FIRs
* are cleared by toggling a rx & tx fir reset bit.
* @param[in] i_target FAPI2 Target
* @param[in] i_tgt FAPI2 Target
* @retval ReturnCode
*/
fapi2::ReturnCode p9_io_dmi_clear_firs(
const fapi2::Target < fapi2::TARGET_TYPE_DMI >& i_target)
fapi2::ReturnCode p9_io_dmi_proc_clear_firs(const DMI_PROC_TGT& i_tgt)
{
FAPI_IMP("I/O Start DMI Clear FIRs");
FAPI_IMP("I/O Start DMI Proc Clear FIRs");

FAPI_TRY(io_tx_fir_reset(i_target), "Tx Reset Failed");
FAPI_TRY(io_dmi_proc_tx_fir_reset(i_tgt), "Tx Reset Failed");

FAPI_TRY(io_rx_fir_reset(i_target), "Rx Reset Failed");
FAPI_TRY(io_dmi_proc_rx_fir_reset(i_tgt), "Rx Reset Failed");

fapi_try_exit:
FAPI_IMP("I/O End DMI Clear FIRs");
FAPI_IMP("I/O End DMI Proc Clear FIRs");
return fapi2::current_err;
}

/**
* @brief This function resets the Rx Firs on a EDI+ DMI
* @param[in] i_target FAPI2 Target
* @param[in] i_tgt FAPI2 Target
* @retval ReturnCode
*/
fapi2::ReturnCode io_rx_fir_reset(
const fapi2::Target < fapi2::TARGET_TYPE_DMI >& i_target)
fapi2::ReturnCode io_dmi_proc_rx_fir_reset(const DMI_PROC_TGT& i_tgt)
{
const uint8_t GRP3 = 3;
const uint8_t LN0 = 0;
uint64_t l_data = 0;

FAPI_TRY(io::read(EDIP_RX_FIR_RESET, i_target, GRP3, LN0, l_data));
FAPI_TRY(io::read(EDIP_RX_FIR_RESET, i_tgt, GRP3, LN0, l_data));

io::set (EDIP_RX_FIR_RESET, 0, l_data);
FAPI_TRY(io::write(EDIP_RX_FIR_RESET, i_target, GRP3, LN0, l_data));
FAPI_TRY(io::write(EDIP_RX_FIR_RESET, i_tgt, GRP3, LN0, l_data));

io::set (EDIP_RX_FIR_RESET, 1, l_data);
FAPI_TRY(io::write(EDIP_RX_FIR_RESET, i_target, GRP3, LN0, l_data));
FAPI_TRY(io::write(EDIP_RX_FIR_RESET, i_tgt, GRP3, LN0, l_data));

io::set (EDIP_RX_FIR_RESET, 0, l_data);
FAPI_TRY(io::write(EDIP_RX_FIR_RESET, i_target, GRP3, LN0, l_data));
FAPI_TRY(io::write(EDIP_RX_FIR_RESET, i_tgt, GRP3, LN0, l_data));

fapi_try_exit:
return fapi2::current_err;
}

/**
* @brief This function resets the Tx Firs on a EDI+ DMI
* @param[in] i_target FAPI2 Target
* @param[in] i_tgt FAPI2 Target
* @retval ReturnCode
*/
fapi2::ReturnCode io_tx_fir_reset(
const fapi2::Target < fapi2::TARGET_TYPE_DMI >& i_target)
fapi2::ReturnCode io_dmi_proc_tx_fir_reset(const DMI_PROC_TGT& i_tgt)
{
const uint8_t GRP3 = 3;
const uint8_t LN0 = 0;
uint64_t l_data = 0;

FAPI_TRY(io::read(EDIP_TX_FIR_RESET, i_target, GRP3, LN0, l_data));
FAPI_TRY(io::read(EDIP_TX_FIR_RESET, i_tgt, GRP3, LN0, l_data));

io::set (EDIP_TX_FIR_RESET, 0, l_data);
FAPI_TRY(io::write(EDIP_TX_FIR_RESET, i_target, GRP3, LN0, l_data));
FAPI_TRY(io::write(EDIP_TX_FIR_RESET, i_tgt, GRP3, LN0, l_data));

io::set (EDIP_TX_FIR_RESET, 1, l_data);
FAPI_TRY(io::write(EDIP_TX_FIR_RESET, i_target, GRP3, LN0, l_data));
FAPI_TRY(io::write(EDIP_TX_FIR_RESET, i_tgt, GRP3, LN0, l_data));

io::set (EDIP_TX_FIR_RESET, 0, l_data);
FAPI_TRY(io::write(EDIP_TX_FIR_RESET, i_target, GRP3, LN0, l_data));
FAPI_TRY(io::write(EDIP_TX_FIR_RESET, i_tgt, GRP3, LN0, l_data));

fapi_try_exit:
return fapi2::current_err;
}


/**
* @brief Clears PHY Rx/Tx FIRs on the DMI Centaur(EDI) specified target. The FIRs
* are cleared by toggling a rx & tx fir reset bit.
* @param[in] i_tgt FAPI2 Target
* @retval ReturnCode
*/
fapi2::ReturnCode p9_io_dmi_cn_clear_firs(const DMI_CN_TGT& i_tgt)
{
FAPI_IMP("I/O Start DMI Proc Clear FIRs");

FAPI_TRY(io_dmi_cn_tx_fir_reset(i_tgt), "Tx Reset Failed");

FAPI_TRY(io_dmi_cn_rx_fir_reset(i_tgt), "Rx Reset Failed");

fapi_try_exit:
FAPI_IMP("I/O End DMI Proc Clear FIRs");
return fapi2::current_err;
}

/**
* @brief This function resets the Rx Firs on a EDI DMI Centaur
* @param[in] i_tgt FAPI2 Target
* @retval ReturnCode
*/
fapi2::ReturnCode io_dmi_cn_rx_fir_reset(const DMI_CN_TGT& i_tgt)
{
const uint8_t GRP0 = 0;
const uint8_t LN0 = 0;
uint64_t l_data = 0;

FAPI_TRY(io::read(EDI_RX_FIR_RESET, i_tgt, GRP0, LN0, l_data));

io::set (EDI_RX_FIR_RESET, 0, l_data);
FAPI_TRY(io::write(EDI_RX_FIR_RESET, i_tgt, GRP0, LN0, l_data));

io::set (EDI_RX_FIR_RESET, 1, l_data);
FAPI_TRY(io::write(EDI_RX_FIR_RESET, i_tgt, GRP0, LN0, l_data));

io::set (EDI_RX_FIR_RESET, 0, l_data);
FAPI_TRY(io::write(EDI_RX_FIR_RESET, i_tgt, GRP0, LN0, l_data));

fapi_try_exit:
return fapi2::current_err;
}

/**
* @brief This function resets the Tx Firs on a EDI DMI Centaur
* @param[in] i_tgt FAPI2 Target
* @retval ReturnCode
*/
fapi2::ReturnCode io_dmi_cn_tx_fir_reset(const DMI_CN_TGT& i_tgt)
{
const uint8_t GRP0 = 0;
const uint8_t LN0 = 0;
uint64_t l_data = 0;

FAPI_TRY(io::read(EDI_TX_FIR_RESET, i_tgt, GRP0, LN0, l_data));

io::set (EDI_TX_FIR_RESET, 0, l_data);
FAPI_TRY(io::write(EDI_TX_FIR_RESET, i_tgt, GRP0, LN0, l_data));

io::set (EDI_TX_FIR_RESET, 1, l_data);
FAPI_TRY(io::write(EDI_TX_FIR_RESET, i_tgt, GRP0, LN0, l_data));

io::set (EDI_TX_FIR_RESET, 0, l_data);
FAPI_TRY(io::write(EDI_TX_FIR_RESET, i_tgt, GRP0, LN0, l_data));

fapi_try_exit:
return fapi2::current_err;
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16 changes: 12 additions & 4 deletions src/import/chips/p9/procedures/hwp/io/p9_io_dmi_clear_firs.H
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Original file line number Diff line number Diff line change
Expand Up @@ -45,8 +45,8 @@
//-----------------------------------------------------------------------------
#include <fapi2.H>

typedef fapi2::ReturnCode (*p9_io_dmi_clear_firs_FP_t)
(const fapi2::Target < fapi2::TARGET_TYPE_DMI >&);
typedef fapi2::Target<fapi2::TARGET_TYPE_DMI> DMI_PROC_TGT;
typedef fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP> DMI_CN_TGT;

extern "C"
{
Expand All @@ -57,8 +57,16 @@ extern "C"
* @param[in] i_target FAPI2 Target
* @retval ReturnCode
*/
fapi2::ReturnCode p9_io_dmi_clear_firs(
const fapi2::Target < fapi2::TARGET_TYPE_DMI >& i_target);
fapi2::ReturnCode p9_io_dmi_proc_clear_firs(const DMI_PROC_TGT& i_tgt);

/**
* @brief Clears PHY Rx/Tx FIRs on the DMI Centaur(EDI) specified target. The FIRs
* are cleared by toggling a rx & tx fir reset bit.
* @param[in] i_target FAPI2 Target
* @retval ReturnCode
*/
fapi2::ReturnCode p9_io_dmi_cn_clear_firs(const DMI_CN_TGT& i_tgt);


} // extern "C"

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