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Fixed the ccs port merge conflicts and added lab code
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Change-Id: Ic4f40a145452f8e95d99e18f040517499a5597ed
Original-Change-Id: I665ea2460a5ace289b17ae868b07a8876b65a0c8
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75236
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81323
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com>
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@Matthickman14 @crgeddes
Matthickman14 authored and crgeddes committed Jul 30, 2019
1 parent 4a69b75 commit afeaf78
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Showing 2 changed files with 16 additions and 15 deletions.
7 changes: 4 additions & 3 deletions src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.C
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Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,8 @@

#include <generic/memory/lib/utils/c_str.H>
#include <generic/memory/lib/utils/find.H>
#include <lib/ccs/ccs.H>
#include <lib/ccs/ccs_traits_nimbus.H>
#include <generic/memory/lib/ccs/ccs.H>
#include <lib/mss_attribute_accessors.H>
#include <lib/dimm/ddr4/mrs_load_ddr4.H>
#include <lib/workarounds/quad_encode_workarounds.H>
Expand Down Expand Up @@ -105,7 +106,7 @@ const std::vector< uint64_t> shadow_regs_traits<6>::REGS =
/// @param[in] i_inst instruction to check for an MRS command
/// @return true iff the command contains an MRS command
///
bool is_command_mrs(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst)
bool is_command_mrs(const ccs::instruction_t& i_inst)
{
// An MRS command is
// 1) at least one chip select active
Expand All @@ -132,7 +133,7 @@ bool is_command_mrs(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst)
/// @param[in] i_inst instruction to check for an MRS command
/// @return true iff the command contains an MRS command
///
bool contains_command_mrs(const std::vector<ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>>& i_inst)
bool contains_command_mrs(const std::vector<ccs::instruction_t>& i_inst)
{
bool l_contains_mrs = false;

Expand Down
24 changes: 12 additions & 12 deletions src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.H
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Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,7 @@
#include <lib/shared/mss_const.H>
#include <generic/memory/lib/utils/c_str.H>
#include <generic/memory/lib/utils/find.H>
#include <lib/ccs/ccs.H>
#include <generic/memory/lib/ccs/ccs.H>
#include <lib/dimm/rank.H>
#include <lib/dimm/ddr4/mrs_load_ddr4.H>
#include <p9_mc_scom_addresses_fld.H>
Expand Down Expand Up @@ -87,21 +87,21 @@ fapi2::ReturnCode check_shadow_register_corruption( const fapi2::Target<fapi2::T
/// @param[in] i_inst instruction to check for an MRS command
/// @return true iff the command contains an MRS command
///
bool is_command_mrs(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst);
bool is_command_mrs(const ccs::instruction_t& i_inst);

///
/// @brief Returns true if a vector of commands contains an MRS command
/// @param[in] i_inst instruction to check for an MRS command
/// @return true iff the command contains an MRS command
///
bool contains_command_mrs(const std::vector<ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>>& i_inst);
bool contains_command_mrs(const std::vector<ccs::instruction_t>& i_inst);

///
/// @brief Converts the CCS instructions to the shadow register configuration
/// @param[in] i_inst CCS instruction to convert
/// @return the register value for the shadow register
///
inline fapi2::buffer<uint64_t> convert_to_shadow_reg(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst)
inline fapi2::buffer<uint64_t> convert_to_shadow_reg(const ccs::instruction_t& i_inst)
{
fapi2::buffer<uint64_t> l_arr0(i_inst.arr0);
mss::reverse(l_arr0);
Expand Down Expand Up @@ -137,7 +137,7 @@ class shadow_regs_traits<0>
/// @return FAPI2_RC_SUCCESS iff OK
///
static inline fapi2::ReturnCode mrs_gen(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst,
ccs::instruction_t& io_inst,
const uint64_t i_rank)
{
constexpr uint8_t LR_2666_MARGIN_ADJUST = 2;
Expand Down Expand Up @@ -188,7 +188,7 @@ class shadow_regs_traits<1>
/// @return FAPI2_RC_SUCCESS iff OK
///
static inline fapi2::ReturnCode mrs_gen(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst,
ccs::instruction_t& io_inst,
const uint64_t i_rank)
{
return mss::ddr4::mrs01(i_target, io_inst, i_rank);
Expand All @@ -214,7 +214,7 @@ class shadow_regs_traits<2>
/// @return FAPI2_RC_SUCCESS iff OK
///
static inline fapi2::ReturnCode mrs_gen(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst,
ccs::instruction_t& io_inst,
const uint64_t i_rank)
{
return mss::ddr4::mrs02(i_target, io_inst, i_rank);
Expand All @@ -240,7 +240,7 @@ class shadow_regs_traits<3>
/// @return FAPI2_RC_SUCCESS iff OK
///
static inline fapi2::ReturnCode mrs_gen(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst,
ccs::instruction_t& io_inst,
const uint64_t i_rank)
{
return mss::ddr4::mrs03(i_target, io_inst, i_rank);
Expand All @@ -266,7 +266,7 @@ class shadow_regs_traits<4>
/// @return FAPI2_RC_SUCCESS iff OK
///
static inline fapi2::ReturnCode mrs_gen(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst,
ccs::instruction_t& io_inst,
const uint64_t i_rank)
{
return mss::ddr4::mrs04(i_target, io_inst, i_rank);
Expand All @@ -292,7 +292,7 @@ class shadow_regs_traits<5>
/// @return FAPI2_RC_SUCCESS iff OK
///
static inline fapi2::ReturnCode mrs_gen(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst,
ccs::instruction_t& io_inst,
const uint64_t i_rank)
{
return mss::ddr4::mrs05(i_target, io_inst, i_rank);
Expand All @@ -318,7 +318,7 @@ class shadow_regs_traits<6>
/// @return FAPI2_RC_SUCCESS iff OK
///
static inline fapi2::ReturnCode mrs_gen(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst,
ccs::instruction_t& io_inst,
const uint64_t i_rank)
{
return mss::ddr4::mrs06(i_target, io_inst, i_rank);
Expand All @@ -342,7 +342,7 @@ fapi2::ReturnCode fix_shadow_register_corruption_mr( const fapi2::Target<fapi2::
{
static_assert( MR <= MAX_MR, "MR instance out of range");

ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> l_inst;
ccs::instruction_t l_inst;
const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target);

// Converts this to DIMM rank. just. in. case.
Expand Down

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