Remove MVPD,MEMD and CENHWIMG section from Axone pnor layout

This commit removes the MVPD, MEMD and CENHWIMG sections from the axone
pnor layout as they are not being used and pnor space is limited.
Along with removing the defintion in the pnor layout xml some code
changes were required to no longer attempt to load the MVPD/MEMD sections.

Change-Id: I20739e30ad497737c0a30b66cc36052c08c11de2
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80295
Reviewed-by: Glenn Miles <milesg@ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>

src/build/buildpnor/pnorLayoutAxone.xml

@@ -93,19 +93,10 @@ Layout Description
         <side>sideless</side>
         <ecc/>
     </section>
-    <section>
-        <description>Module VPD (576K)</description>
-        <eyeCatch>MVPD</eyeCatch>
-        <!--NOTE: MUST update standalone.simics if offset changes -->
-        <physicalOffset>0x31000</physicalOffset>
-        <physicalRegionSize>0x90000</physicalRegionSize>
-        <side>sideless</side>
-        <ecc/>
-    </section>
     <section>
         <description>Hostboot Base (1MB)</description>
         <eyeCatch>HBB</eyeCatch>
-        <physicalOffset>0xC1000</physicalOffset>
+        <physicalOffset>0x31000</physicalOffset>
         <physicalRegionSize>0x100000</physicalRegionSize>
         <side>sideless</side>
         <sha512Version/>
@@ -114,7 +105,7 @@ Layout Description
     <section>
         <description>Hostboot Data (2MB)</description>
         <eyeCatch>HBD</eyeCatch>
-        <physicalOffset>0x1C1000</physicalOffset>
+        <physicalOffset>0x131000</physicalOffset>
         <physicalRegionSize>0x200000</physicalRegionSize>
         <sha512Version/>
         <side>sideless</side>
@@ -123,7 +114,7 @@ Layout Description
     <section>
         <description>Hostboot Extended image (17.77MB w/o ECC)</description>
         <eyeCatch>HBI</eyeCatch>
-        <physicalOffset>0x3C1000</physicalOffset>
+        <physicalOffset>0x331000</physicalOffset>
         <physicalRegionSize>0x1400000</physicalRegionSize>
         <sha512Version/>
         <side>sideless</side>
@@ -132,7 +123,7 @@ Layout Description
     <section>
         <description>SBE-IPL (Staging Area) (752K)</description>
         <eyeCatch>SBE</eyeCatch>
-        <physicalOffset>0x17C1000</physicalOffset>
+        <physicalOffset>0x1731000</physicalOffset>
         <physicalRegionSize>0xBC000</physicalRegionSize>
         <sha512perEC/>
         <sha512Version/>
@@ -142,7 +133,7 @@ Layout Description
     <section>
         <description>HCODE Ref Image (1.125MB)</description>
         <eyeCatch>HCODE</eyeCatch>
-        <physicalOffset>0x187D000</physicalOffset>
+        <physicalOffset>0x17ED000</physicalOffset>
         <physicalRegionSize>0x120000</physicalRegionSize>
         <sha512Version/>
         <side>sideless</side>
@@ -151,7 +142,7 @@ Layout Description
     <section>
         <description>Hostboot Runtime Services for Sapphire (8.0MB)</description>
         <eyeCatch>HBRT</eyeCatch>
-        <physicalOffset>0x199D000</physicalOffset>
+        <physicalOffset>0x190D000</physicalOffset>
         <physicalRegionSize>0x800000</physicalRegionSize>
         <sha512Version/>
         <side>sideless</side>
@@ -160,7 +151,7 @@ Layout Description
     <section>
         <description>Payload (19.875MB)</description>
         <eyeCatch>PAYLOAD</eyeCatch>
-        <physicalOffset>0x219D000</physicalOffset>
+        <physicalOffset>0x210D000</physicalOffset>
         <physicalRegionSize>0x13E0000</physicalRegionSize>
         <sha512Version/>
         <side>sideless</side>
@@ -169,7 +160,7 @@ Layout Description
     <section>
         <description>Special PNOR Test Space (36K)</description>
         <eyeCatch>TEST</eyeCatch>
-        <physicalOffset>0x357D000</physicalOffset>
+        <physicalOffset>0x34ED000</physicalOffset>
         <physicalRegionSize>0x9000</physicalRegionSize>
         <testonly/>
         <side>sideless</side>
@@ -180,7 +171,7 @@ Layout Description
              from skipping header. Signing is forced in build pnor phase -->
         <description>Special PNOR Test Space with Header (36K)</description>
         <eyeCatch>TESTRO</eyeCatch>
-        <physicalOffset>0x3586000</physicalOffset>
+        <physicalOffset>0x34F6000</physicalOffset>
         <physicalRegionSize>0x9000</physicalRegionSize>
         <side>sideless</side>
         <testonly/>
@@ -191,7 +182,7 @@ Layout Description
     <section>
         <description>Hostboot Bootloader (28K)</description>
         <eyeCatch>HBBL</eyeCatch>
-        <physicalOffset>0x358F000</physicalOffset>
+        <physicalOffset>0x34FF000</physicalOffset>
         <!-- Physical Size includes Header rounded to ECC valid size -->
         <!-- Max size of actual HBBL content is 20K and 22.5K with ECC -->
         <physicalRegionSize>0x7000</physicalRegionSize>
@@ -202,23 +193,23 @@ Layout Description
     <section>
         <description>Ref Image Ring Overrides (20K)</description>
         <eyeCatch>RINGOVD</eyeCatch>
-        <physicalOffset>0x3596000</physicalOffset>
+        <physicalOffset>0x3506000</physicalOffset>
         <physicalRegionSize>0x5000</physicalRegionSize>
         <side>sideless</side>
         <ecc/>
     </section>
     <section>
         <description>SecureBoot Key Transition Partition (16K)</description>
         <eyeCatch>SBKT</eyeCatch>
-        <physicalOffset>0x359B000</physicalOffset>
+        <physicalOffset>0x350B000</physicalOffset>
         <physicalRegionSize>0x4000</physicalRegionSize>
         <side>sideless</side>
         <ecc/>
     </section>
     <section>
         <description>OCC Lid (1.125M)</description>
         <eyeCatch>OCC</eyeCatch>
-        <physicalOffset>0x359F000</physicalOffset>
+        <physicalOffset>0x350F000</physicalOffset>
         <physicalRegionSize>0x120000</physicalRegionSize>
         <sha512Version/>
         <side>sideless</side>
@@ -229,7 +220,7 @@ Layout Description
         <!-- We need 266KB per module sort, going to support
              40 tables by default, plus ECC  -->
         <eyeCatch>WOFDATA</eyeCatch>
-        <physicalOffset>0x36BF000</physicalOffset>
+        <physicalOffset>0x362F000</physicalOffset>
         <physicalRegionSize>0x600000</physicalRegionSize>
         <side>sideless</side>
         <sha512Version/>
@@ -238,42 +229,24 @@ Layout Description
     <section>
         <description>FIRDATA (12K)</description>
         <eyeCatch>FIRDATA</eyeCatch>
-        <physicalOffset>0x3CBF000</physicalOffset>
+        <physicalOffset>0x3C2F000</physicalOffset>
         <physicalRegionSize>0x3000</physicalRegionSize>
         <side>sideless</side>
         <ecc/>
     </section>
-    <section>
-        <description>Memory Data (128K)</description>
-        <eyeCatch>MEMD</eyeCatch>
-        <physicalOffset>0x3CC2000</physicalOffset>
-        <physicalRegionSize>0x20000</physicalRegionSize>
-        <side>sideless</side>
-        <sha512Version/>
-        <ecc/>
-    </section>
     <section>
         <description>Secureboot Test Load (12K)</description>
         <eyeCatch>TESTLOAD</eyeCatch>
-        <physicalOffset>0x3CE2000</physicalOffset>
+        <physicalOffset>0x3C32000</physicalOffset>
         <physicalRegionSize>0x3000</physicalRegionSize>
         <side>sideless</side>
         <sha512Version/>
         <ecc/>
     </section>
-    <section>
-        <description>Centaur Hw Ref Image (12K)</description>
-        <eyeCatch>CENHWIMG</eyeCatch>
-        <physicalOffset>0x3CE5000</physicalOffset>
-        <physicalRegionSize>0x3000</physicalRegionSize>
-        <sha512Version/>
-        <side>sideless</side>
-        <ecc/>
-    </section>
     <section>
         <description>Secure Boot (144K)</description>
         <eyeCatch>SECBOOT</eyeCatch>
-        <physicalOffset>0x3CE8000</physicalOffset>
+        <physicalOffset>0x3C35000</physicalOffset>
         <physicalRegionSize>0x24000</physicalRegionSize>
         <side>sideless</side>
         <ecc/>
@@ -282,7 +255,7 @@ Layout Description
     <section>
         <description>Open CAPI Memory Buffer (OCMB) Firmware (1164K)</description>
         <eyeCatch>OCMBFW</eyeCatch>
-        <physicalOffset>0x3D0C000</physicalOffset>
+        <physicalOffset>0x3C59000</physicalOffset>
         <physicalRegionSize>0x123000</physicalRegionSize>
         <side>sideless</side>
         <sha512Version/>
@@ -292,7 +265,7 @@ Layout Description
     <section>
         <description>HDAT Data (16K)</description>
         <eyeCatch>HDAT</eyeCatch>
-        <physicalOffset>0x3E2F000</physicalOffset>
+        <physicalOffset>0x3D7C000</physicalOffset>
         <physicalRegionSize>0x4000</physicalRegionSize>
         <side>sideless</side>
         <sha512Version/>
@@ -302,7 +275,7 @@ Layout Description
         <!-- NOTE must update standalone.simics if EECACHE offset changes-->
         <description>Eeprom Cache(512K)</description>
         <eyeCatch>EECACHE</eyeCatch>
-        <physicalOffset>0x3E33000</physicalOffset>
+        <physicalOffset>0x3D80000</physicalOffset>
         <physicalRegionSize>0x80000</physicalRegionSize>
         <side>sideless</side>
         <ecc/>

src/build/mkrules/hbfw/img/makefile

@@ -213,16 +213,16 @@ BUILD_TYPE_PARAMS = --build-type fspbuild
 .endif
 
 # Decide which images to use for each PNOR layout
-GEN_COMMON_BIN_FILES = HBBL=${HBBL_IMG},HBB=${HBB_IMG},HBI=${HBI_IMG},HBRT=${HBRT_IMG},HBEL=EMPTY,GUARD=EMPTY,MVPD=EMPTY,RINGOVD=EMPTY,SBKT=EMPTY
+GEN_COMMON_BIN_FILES = HBBL=${HBBL_IMG},HBB=${HBB_IMG},HBI=${HBI_IMG},HBRT=${HBRT_IMG},HBEL=EMPTY,GUARD=EMPTY,RINGOVD=EMPTY,SBKT=EMPTY
 GEN_STANDALONE_BIN_FILES = ${GEN_COMMON_BIN_FILES},TEST=EMPTY,TESTRO=EMPTY,TESTLOAD=EMPTY,PAYLOAD=EMPTY,FIRDATA=EMPTY
 .if (${FAKEPNOR} == "")
     # Parameters passed into GEN_PNOR_IMAGE_SCRIPT.
     .if (${PNOR_LAYOUT_SELECTED} == "STANDALONE")
-        GEN_DEFAULT_BIN_FILES = ${GEN_STANDALONE_BIN_FILES},MEMD=${${ZZ_MEMD_IMG}:P},CVPD=EMPTY,DJVPD=EMPTY
+        GEN_DEFAULT_BIN_FILES = ${GEN_STANDALONE_BIN_FILES},MEMD=${${ZZ_MEMD_IMG}:P},CVPD=EMPTY,DJVPD=EMPTY,MVPD=EMPTY
     .elif(${PNOR_LAYOUT_SELECTED} == "AXONE")
-    GEN_DEFAULT_BIN_FILES = ${GEN_STANDALONE_BIN_FILES},EECACHE=EMPTY,MEMD=${${ZZ_MEMD_IMG}:P},OCMBFW=${${OCMBFW_IMG}:P}
+    GEN_DEFAULT_BIN_FILES = ${GEN_STANDALONE_BIN_FILES},EECACHE=EMPTY,OCMBFW=${${OCMBFW_IMG}:P}
     .else
-        GEN_DEFAULT_BIN_FILES = ${GEN_COMMON_BIN_FILES},MEMD=${${ZZ_MEMD_IMG}:P},CVPD=EMPTY,DJVPD=EMPTY
+        GEN_DEFAULT_BIN_FILES = ${GEN_COMMON_BIN_FILES},MEMD=${${ZZ_MEMD_IMG}:P},CVPD=EMPTY,DJVPD=EMPTY,MVPD=EMPTY
     .endif
     DEFAULT_PARAMS = --build-all --emit-eccless ${TARGET_TEST:b--test} ${HB_STANDALONE:b--hb-standalone} \
                      ${CONFIG_SECUREBOOT:b--secureboot} --systemBinFiles ${GEN_DEFAULT_BIN_FILES} \
@@ -374,7 +374,6 @@ AXONE_HCODE_IMG = ${ENGD_SRCPATH:Fp9a.hw_ref_image.bin}
 
 CUMULUS_CENHWIMG_IMG = ${ENGD_SRCPATH:Fcen.hw_ref_image.bin}
 NIMBUS_CENHWIMG_IMG = cen.hw_ref_image.bin.fake
-AXONE_CENHWIMG_IMG = cen.hw_ref_image.bin.fake
 NIMBUS_OCC_IMG = ${bb}/images/ppc/lab/fs/p9le/rootfs/opt/extucode/81e00430.lid
 CUMULUS_OCC_IMG = ${bb}/images/ppc/lab/fs/p9le/rootfs/opt/extucode/81e00430.lid
 AXONE_OCC_IMG = ${bb}/images/ppc/lab/fs/p9le/rootfs/opt/extucode/81e00430.lid
@@ -410,7 +409,6 @@ CUMULUS_HCODE_FINAL_IMG = CUMULUS.HCODE.bin
 AXONE_HCODE_FINAL_IMG = AXONE.HCODE.bin
 CUMULUS_CENHWIMG_FINAL_IMG = CUMULUS.CENHWIMG.bin
 NIMBUS_CENHWIMG_FINAL_IMG = NIMBUS.CENHWIMG.bin
-AXONE_CENHWIMG_FINAL_IMG = AXONE.CENHWIMG.bin
 NIMBUS_SBE_FINAL_IMG = NIMBUS.SBE.bin
 CUMULUS_SBE_FINAL_IMG = CUMULUS.SBE.bin
 AXONE_SBE_FINAL_IMG = AXONE.SBE.bin
@@ -440,12 +438,12 @@ ZZ2UGEN4_HBD_FINAL_IMG = ZZ-2U-GEN4.HBD.bin
         GEN_NIMBUS_BIN_FILES = NIMBUS:SBE=${${NIMBUS_SBE_IMG}:P},HCODE=${${NIMBUS_HCODE_IMG}:P},OCC=${${NIMBUS_OCC_IMG}:P},HBD=${${NIMBUS_HBD_IMG}:P},CENHWIMG=${NIMBUS_CENHWIMG_IMG}
         GEN_CUMULUS_BIN_FILES = CUMULUS:SBE=${${CUMULUS_SBE_IMG}:P},HCODE=${${CUMULUS_HCODE_IMG}:P},OCC=${${CUMULUS_OCC_IMG}:P},HBD=${${CUMULUS_HBD_IMG}:P},CENHWIMG=${${CUMULUS_CENHWIMG_IMG}:P}
         GEN_CUMULUS_CDIMM_BIN_FILES = CUMULUS_CDIMM:SBE=${${CUMULUS_SBE_IMG}:P},HCODE=${${CUMULUS_HCODE_IMG}:P},OCC=${${CUMULUS_OCC_IMG}:P},HBD=${${CUMULUS_CDIMM_HBD_IMG}:P},CENHWIMG=${${CUMULUS_CENHWIMG_IMG}:P}
-        GEN_AXONE_BIN_FILES = AXONE:SBE=${${AXONE_SBE_IMG}:P},HCODE=${${AXONE_HCODE_IMG}:P},OCC=${${AXONE_OCC_IMG}:P},HBD=${${AXONE_HBD_IMG}:P},CENHWIMG=${AXONE_CENHWIMG_IMG}
+        GEN_AXONE_BIN_FILES = AXONE:SBE=${${AXONE_SBE_IMG}:P},HCODE=${${AXONE_HCODE_IMG}:P},OCC=${${AXONE_OCC_IMG}:P},HBD=${${AXONE_HBD_IMG}:P}
     .else
         GEN_NIMBUS_BIN_FILES = NIMBUS:SBE=${${NIMBUS_SBE_IMG}:P},HCODE=${${NIMBUS_HCODE_IMG}:P},OCC=${${NIMBUS_OCC_IMG}:P},HBD=${${NIMBUS_HBD_IMG}:P},CENHWIMG=${NIMBUS_CENHWIMG_IMG}
         GEN_CUMULUS_BIN_FILES = CUMULUS:SBE=${${CUMULUS_SBE_IMG}:P},HCODE=${${CUMULUS_HCODE_IMG}:P},OCC=${${CUMULUS_OCC_IMG}:P},HBD=${${CUMULUS_HBD_IMG}:P},CENHWIMG=${${CUMULUS_CENHWIMG_IMG}:P}
         GEN_CUMULUS_CDIMM_BIN_FILES = CUMULUS_CDIMM:SBE=${${CUMULUS_SBE_IMG}:P},HCODE=${${CUMULUS_HCODE_IMG}:P},OCC=${${CUMULUS_OCC_IMG}:P},HBD=${${CUMULUS_CDIMM_HBD_IMG}:P},CENHWIMG=${${CUMULUS_CENHWIMG_IMG}:P}
-        GEN_AXONE_BIN_FILES = AXONE:SBE=${${AXONE_SBE_IMG}:P},HCODE=${${AXONE_HCODE_IMG}:P},OCC=${${AXONE_OCC_IMG}:P},HBD=${${AXONE_HBD_IMG}:P},CENHWIMG=${AXONE_CENHWIMG_IMG}
+        GEN_AXONE_BIN_FILES = AXONE:SBE=${${AXONE_SBE_IMG}:P},HCODE=${${AXONE_HCODE_IMG}:P},OCC=${${AXONE_OCC_IMG}:P},HBD=${${AXONE_HBD_IMG}:P}
 
     .endif
     GEN_ZZ_BIN_FILES = ZZ:WOFDATA=${${ZZ_WOFDATA_IMG}:P},MEMD=${${ZZ_MEMD_IMG}:P},HBD=${${ZZ_HBD_IMG}:P}
@@ -473,7 +471,7 @@ ZZ2UGEN4_HBD_FINAL_IMG = ZZ-2U-GEN4.HBD.bin
     GEN_NIMBUS_BIN_FILES = NIMBUS:HCODE=${${NIMBUS_HCODE_IMG}:P},HBD=${${NIMBUS_VPO_HBD_IMG}:P},CENHWIMG=EMPTY
     GEN_CUMULUS_BIN_FILES = CUMULUS:HCODE=${${CUMULUS_HCODE_IMG}:P},CENHWIMG=${${CUMULUS_CENHWIMG_IMG}:P}
     GEN_CUMULUS_CDIMM_BIN_FILES = CUMULUS:HCODE=${${CUMULUS_HCODE_IMG}:P},CENHWIMG=${${CUMULUS_CENHWIMG_IMG}:P}
-    GEN_AXONE_BIN_FILES = AXONE:HCODE=${${AXONE_HCODE_IMG}:P},HBD=${${AXONE_VPO_HBD_IMG}:P},CENHWIMG=EMPTY
+    GEN_AXONE_BIN_FILES = AXONE:HCODE=${${AXONE_HCODE_IMG}:P},HBD=${${AXONE_VPO_HBD_IMG}:P}
     SYSTEM_SPECIFIC_PARAMS = --pnorLayout ${PNOR_LAYOUT} \
                              --systemBinFiles ${GEN_NIMBUS_BIN_FILES} \
                              --systemBinFiles ${GEN_CUMULUS_BIN_FILES} \
@@ -501,12 +499,12 @@ gen_system_specific_images: build_sbe_partitions .PMAKE
 .if (${PNOR_LAYOUT_SELECTED} == "FSP")
     HOSTBOOT_DEFAULT_SECTIONS = HBBL=${HBBL_FINAL_IMG},HBB=${HBB_FINAL_IMG},HBI=${HBI_FINAL_IMG},HBRT=${HBRT_FINAL_IMG},HBEL=${HBEL_FINAL_IMG},GUARD=${GUARD_FINAL_IMG},MVPD=${MVPD_FINAL_IMG},RINGOVD=${RINGOVD_FINAL_IMG},SBKT=${SBKT_FINAL_IMG}
 .else
-    HOSTBOOT_DEFAULT_SECTIONS = HBBL=${HBBL_FINAL_IMG},HBB=${HBB_FINAL_IMG},HBI=${HBI_FINAL_IMG},HBRT=${HBRT_FINAL_IMG},TEST=${TEST_FINAL_IMG},TESTRO=${TESTRO_FINAL_IMG},TESTLOAD=${TESTLOAD_FINAL_IMG},HBEL=${HBEL_FINAL_IMG},GUARD=${GUARD_FINAL_IMG},PAYLOAD=${PAYLOAD_FINAL_IMG},MVPD=${MVPD_FINAL_IMG},RINGOVD=${RINGOVD_FINAL_IMG},SBKT=${SBKT_FINAL_IMG},FIRDATA=${FIRDATA_FINAL_IMG}
+    HOSTBOOT_DEFAULT_SECTIONS = HBBL=${HBBL_FINAL_IMG},HBB=${HBB_FINAL_IMG},HBI=${HBI_FINAL_IMG},HBRT=${HBRT_FINAL_IMG},TEST=${TEST_FINAL_IMG},TESTRO=${TESTRO_FINAL_IMG},TESTLOAD=${TESTLOAD_FINAL_IMG},HBEL=${HBEL_FINAL_IMG},GUARD=${GUARD_FINAL_IMG},PAYLOAD=${PAYLOAD_FINAL_IMG},RINGOVD=${RINGOVD_FINAL_IMG},SBKT=${SBKT_FINAL_IMG},FIRDATA=${FIRDATA_FINAL_IMG}
 .endif
-NIMBUS_SECT = HBD=${NIMBUS_HBD_FINAL_IMG},SBE=${NIMBUS_SBE_FINAL_IMG},HCODE=${NIMBUS_HCODE_FINAL_IMG},OCC=${NIMBUS_OCC_FINAL_IMG},WOFDATA=${ZZ_WOFDATA_FINAL_IMG},CENHWIMG=${NIMBUS_CENHWIMG_FINAL_IMG},MEMD=${ZZ_MEMD_FINAL_IMG},CVPD=${CVPD_FINAL_IMG},DJVPD=${DJVPD_FINAL_IMG}
-CUMULUS_SECT = HBD=${CUMULUS_HBD_FINAL_IMG},SBE=${CUMULUS_SBE_FINAL_IMG},HCODE=${CUMULUS_HCODE_FINAL_IMG},OCC=${CUMULUS_OCC_FINAL_IMG},WOFDATA=${ZEPPELIN_WOFDATA_FINAL_IMG},CENHWIMG=${CUMULUS_CENHWIMG_FINAL_IMG},MEMD=${ZEPPELIN_MEMD_FINAL_IMG},CVPD=${CVPD_FINAL_IMG},DJVPD=${DJVPD_FINAL_IMG}
-CUMULUS_CDIMM_SECT = HBD=${CUMULUS_CDIMM_HBD_FINAL_IMG},SBE=${CUMULUS_SBE_FINAL_IMG},HCODE=${CUMULUS_HCODE_FINAL_IMG},OCC=${CUMULUS_OCC_FINAL_IMG},WOFDATA=${ZEPPELIN_WOFDATA_FINAL_IMG},CENHWIMG=${CUMULUS_CENHWIMG_FINAL_IMG},MEMD=${MEMD_FINAL_IMG},CVPD=${CVPD_FINAL_IMG},DJVPD=${DJVPD_FINAL_IMG}
-AXONE_SECT = HBD=${AXONE_HBD_FINAL_IMG},SBE=${AXONE_SBE_FINAL_IMG},HCODE=${AXONE_HCODE_FINAL_IMG},OCC=${AXONE_OCC_FINAL_IMG},WOFDATA=${ZEPPELIN_WOFDATA_FINAL_IMG},CENHWIMG=${AXONE_CENHWIMG_FINAL_IMG},EECACHE=${EECACHE_FINAL_IMG},FIRDATA=${FIRDATA_FINAL_IMG},MEMD=${MEMD_FINAL_IMG},OCMBFW=${OCMBFW_FINAL_IMG}
+NIMBUS_SECT = HBD=${NIMBUS_HBD_FINAL_IMG},SBE=${NIMBUS_SBE_FINAL_IMG},HCODE=${NIMBUS_HCODE_FINAL_IMG},OCC=${NIMBUS_OCC_FINAL_IMG},WOFDATA=${ZZ_WOFDATA_FINAL_IMG},CENHWIMG=${NIMBUS_CENHWIMG_FINAL_IMG},MEMD=${ZZ_MEMD_FINAL_IMG},CVPD=${CVPD_FINAL_IMG},DJVPD=${DJVPD_FINAL_IMG},MVPD=${MVPD_FINAL_IMG}
+CUMULUS_SECT = HBD=${CUMULUS_HBD_FINAL_IMG},SBE=${CUMULUS_SBE_FINAL_IMG},HCODE=${CUMULUS_HCODE_FINAL_IMG},OCC=${CUMULUS_OCC_FINAL_IMG},WOFDATA=${ZEPPELIN_WOFDATA_FINAL_IMG},CENHWIMG=${CUMULUS_CENHWIMG_FINAL_IMG},MEMD=${ZEPPELIN_MEMD_FINAL_IMG},CVPD=${CVPD_FINAL_IMG},DJVPD=${DJVPD_FINAL_IMG},MVPD=${MVPD_FINAL_IMG}
+CUMULUS_CDIMM_SECT = HBD=${CUMULUS_CDIMM_HBD_FINAL_IMG},SBE=${CUMULUS_SBE_FINAL_IMG},HCODE=${CUMULUS_HCODE_FINAL_IMG},OCC=${CUMULUS_OCC_FINAL_IMG},WOFDATA=${ZEPPELIN_WOFDATA_FINAL_IMG},CENHWIMG=${CUMULUS_CENHWIMG_FINAL_IMG},MEMD=${MEMD_FINAL_IMG},CVPD=${CVPD_FINAL_IMG},DJVPD=${DJVPD_FINAL_IMG},MVPD=${MVPD_FINAL_IMG}
+AXONE_SECT = HBD=${AXONE_HBD_FINAL_IMG},SBE=${AXONE_SBE_FINAL_IMG},HCODE=${AXONE_HCODE_FINAL_IMG},OCC=${AXONE_OCC_FINAL_IMG},WOFDATA=${ZEPPELIN_WOFDATA_FINAL_IMG},EECACHE=${EECACHE_FINAL_IMG},FIRDATA=${FIRDATA_FINAL_IMG},OCMBFW=${OCMBFW_FINAL_IMG}
 
 
 .if (${PNOR_LAYOUT_SELECTED} == "AXONE")
@@ -531,7 +529,7 @@ PNOR_IMG_INFO = \
     NIMBUS_SECT = HBD=${NIMBUS_HBD_FINAL_IMG},HCODE=${NIMBUS_HCODE_FINAL_IMG},CENHWIMG=${NIMBUS_CENHWIMG_FINAL_IMG}
     CUMULUS_SECT = HBD=${CUMULUS_HBD_FINAL_IMG},HCODE=${CUMULUS_HCODE_FINAL_IMG},CENHWIMG=${CUMULUS_CENHWIMG_FINAL_IMG}
     CUMULUS_CDIMM_SECT = HBD=${CUMULUS_CDIMM_HBD_FINAL_IMG},HCODE=${CUMULUS_HCODE_FINAL_IMG},CENHWIMG=${CUMULUS_CENHWIMG_FINAL_IMG}
-    AXONE_SECT = HBD=${AXONE_HBD_FINAL_IMG},HCODE=${AXONE_HCODE_FINAL_IMG},CENHWIMG=${AXONE_CENHWIMG_FINAL_IMG}
+    AXONE_SECT = HBD=${AXONE_HBD_FINAL_IMG},HCODE=${AXONE_HCODE_FINAL_IMG}
     PNOR_IMG_INFO = \
         ${FAKEPNOR}:${PNOR_LAYOUT}:${NIMBUS_SECT}:${CUMULUS_SECT}:${CUMULUS_CDIMM_SECT},${HOSTBOOT_DEFAULT_SECTIONS},${AXONE_SECT} \
         ${FIPS_PNOR_INFO}

src/build/simics/standalone.simics

@@ -57,8 +57,8 @@ if ($hb_skip_vpd_preload == 0) {
 if ($hb_mode == 0) {
     $eccPreload = (lookup-file "%simics%/eecache_prebuilt.bin.ecc")
     # NOTE must change offset if PNOR layout changes EECACHE offsets
-    echo "    - Loading prebuilt EECACHE "+$eccPreload+" at 0x3E33000 in PNOR"
-    ($hb_pnor).load-file $eccPreload 0x3E33000
+    echo "    - Loading prebuilt EECACHE "+$eccPreload+" at 0x3D80000 in PNOR"
+    ($hb_pnor).load-file $eccPreload 0x3D80000
 }
 
 

src/usr/fapi2/test/fapi2GetVpdTest.H

@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2016,2019                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -46,7 +46,7 @@ public:
 
 void testGetVPD(void)
 {
-#ifdef CONFIG_SECUREBOOT
+#if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE)
     errlHndl_t pError=NULL;
     do
     {
@@ -71,7 +71,7 @@ void testGetVPD(void)
         testGetVPD_DQ();
 
         testGetVPD_CK();
-#ifdef CONFIG_SECUREBOOT
+#if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE)
         pError = PNOR::unloadSecureSection(PNOR::MEMD);
         if(pError)
         {

src/usr/isteps/istep07/call_mss_eff_config.C

@@ -180,13 +180,13 @@ void*    call_mss_eff_config( void *io_pArgs )
 {
     IStepError l_StepError;
     errlHndl_t l_err = nullptr;
-#ifdef CONFIG_SECUREBOOT
+#if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE)
     auto memdLoaded = false;
 #endif
 
     do {
 
-    #ifdef CONFIG_SECUREBOOT
+    #if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE)
     // MEMD used by p9_mss_eff_config HWP
     l_err = loadSecureSection(PNOR::MEMD);
     if (l_err)
@@ -577,7 +577,7 @@ void*    call_mss_eff_config( void *io_pArgs )
 
     } while (0);
 
-    #ifdef CONFIG_SECUREBOOT
+    #if (defined CONFIG_SECUREBOOT && ! defined CONFIG_AXONE)
     if(memdLoaded)
     {
         l_err = unloadSecureSection(PNOR::MEMD);