Skip to content

Commit

Permalink
Fix the encoding of alu instructions
Browse files Browse the repository at this point in the history 
Spec:https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst
  • Loading branch information
@ChunyuLiao
ChunyuLiao committed Nov 22, 2022
1 parent 6c12852 commit ad21787
Show file tree
Hide file tree
Showing 34 changed files with 138 additions and 138 deletions.
8 changes: 4 additions & 4 deletions llvm/lib/Target/RISCV/RISCVInstrFormatsCOREV.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -128,7 +128,7 @@ class RVInstAlu_rri<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
let Opcode = OPC_CUSTOM2.Value;
let Opcode = OPC_CUSTOM1.Value;
}

class RVInstAlu_rr<bits<7> funct7, bits<3> funct3, dag outs, dag ins,
Expand All @@ -143,7 +143,7 @@ class RVInstAlu_rr<bits<7> funct7, bits<3> funct3, dag outs, dag ins,
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
let Opcode = OPC_OP.Value;
let Opcode = OPC_CUSTOM1.Value;
}

class RVInstAlu_ri<bits<7> funct7, bits<3> funct3, dag outs, dag ins,
Expand All @@ -158,7 +158,7 @@ class RVInstAlu_ri<bits<7> funct7, bits<3> funct3, dag outs, dag ins,
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
let Opcode = OPC_OP.Value;
let Opcode = OPC_CUSTOM1.Value;
}

class RVInstAlu_r<bits<7> funct7, bits<3> funct3, dag outs, dag ins,
Expand All @@ -173,7 +173,7 @@ class RVInstAlu_r<bits<7> funct7, bits<3> funct3, dag outs, dag ins,
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
let Opcode = OPC_OP.Value;
let Opcode = OPC_CUSTOM1.Value;
}

class RVInstImmBranch<bits<3> funct3, dag outs, dag ins,
Expand Down
62 changes: 31 additions & 31 deletions llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -181,106 +181,106 @@ let Predicates = [HasExtXCoreVMac], hasSideEffects = 0, mayLoad = 0, mayStore =

let Predicates = [HasExtXCoreVAlu], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
// General ALU Operations
def CV_ABS : RVInstAlu_r<0b0000010, 0b000, (outs GPR:$rd), (ins GPR:$rs1),
def CV_ABS : RVInstAlu_r<0b0101000, 0b011, (outs GPR:$rd), (ins GPR:$rs1),
"cv.abs", "$rd, $rs1", []>,
Sched<[]>;
def CV_SLET : RVInstAlu_rr<0b0000010, 0b010, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
def CV_SLET : RVInstAlu_rr<0b0101001, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
"cv.slet", "$rd, $rs1, $rs2", []>,
Sched<[]>;
def CV_SLETU : RVInstAlu_rr<0b0000010, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
def CV_SLETU : RVInstAlu_rr<0b0101010, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
"cv.sletu", "$rd, $rs1, $rs2", []>,
Sched<[]>;
def CV_MIN : RVInstAlu_rr<0b0000010, 0b100, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
def CV_MIN : RVInstAlu_rr<0b0101011, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
"cv.min", "$rd, $rs1, $rs2", []>,
Sched<[]>;
def CV_MINU : RVInstAlu_rr<0b0000010, 0b101, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
def CV_MINU : RVInstAlu_rr<0b0101100, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
"cv.minu", "$rd, $rs1, $rs2", []>,
Sched<[]>;
def CV_MAX : RVInstAlu_rr<0b0000010, 0b110, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
def CV_MAX : RVInstAlu_rr<0b0101101, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
"cv.max", "$rd, $rs1, $rs2", []>,
Sched<[]>;
def CV_MAXU : RVInstAlu_rr<0b0000010, 0b111, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
def CV_MAXU : RVInstAlu_rr<0b0101110, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
"cv.maxu", "$rd, $rs1, $rs2", []>,
Sched<[]>;
def CV_EXTHS : RVInstAlu_r<0b0001000, 0b100, (outs GPR:$rd), (ins GPR:$rs1),
def CV_EXTHS : RVInstAlu_r<0b0101111, 0b011, (outs GPR:$rd), (ins GPR:$rs1),
"cv.exths", "$rd, $rs1", []>,
Sched<[]>;
def CV_EXTHZ : RVInstAlu_r<0b0001000, 0b101, (outs GPR:$rd), (ins GPR:$rs1),
def CV_EXTHZ : RVInstAlu_r<0b0110000, 0b011, (outs GPR:$rd), (ins GPR:$rs1),
"cv.exthz", "$rd, $rs1", []>,
Sched<[]>;
def CV_EXTBS : RVInstAlu_r<0b0001000, 0b110, (outs GPR:$rd), (ins GPR:$rs1),
def CV_EXTBS : RVInstAlu_r<0b0110001, 0b011, (outs GPR:$rd), (ins GPR:$rs1),
"cv.extbs", "$rd, $rs1", []>,
Sched<[]>;
def CV_EXTBZ : RVInstAlu_r<0b0001000, 0b111, (outs GPR:$rd), (ins GPR:$rs1),
def CV_EXTBZ : RVInstAlu_r<0b0110010, 0b011, (outs GPR:$rd), (ins GPR:$rs1),
"cv.extbz", "$rd, $rs1", []>,
Sched<[]>;

def CV_CLIP : RVInstAlu_ri<0b0001010, 0b001, (outs GPR:$rd), (ins GPR:$rs1, uimm5:$imm5),
def CV_CLIP : RVInstAlu_ri<0b0111000, 0b011, (outs GPR:$rd), (ins GPR:$rs1, uimm5:$imm5),
"cv.clip", "$rd, $rs1, $imm5", []>,
Sched<[]>;
def CV_CLIPU : RVInstAlu_ri<0b0001010, 0b010, (outs GPR:$rd), (ins GPR:$rs1, uimm5:$imm5),
def CV_CLIPU : RVInstAlu_ri<0b0111001, 0b011, (outs GPR:$rd), (ins GPR:$rs1, uimm5:$imm5),
"cv.clipu", "$rd, $rs1, $imm5", []>,
Sched<[]>;
def CV_CLIPR : RVInstAlu_rr<0b0001010, 0b101, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
def CV_CLIPR : RVInstAlu_rr<0b0111010, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
"cv.clipr", "$rd, $rs1, $rs2", []>,
Sched<[]>;
def CV_CLIPUR : RVInstAlu_rr<0b0001010, 0b110, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
def CV_CLIPUR : RVInstAlu_rr<0b0111011, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
"cv.clipur", "$rd, $rs1, $rs2", []>,
Sched<[]>;

def CV_ADDN : RVInstAlu_rri<0b00, 0b010, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
"cv.addn", "$rd, $rs1, $rs2, $imm5", []>,
Sched<[]>;
def CV_ADDUN : RVInstAlu_rri<0b10, 0b010, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
def CV_ADDUN : RVInstAlu_rri<0b01, 0b010, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
"cv.addun", "$rd, $rs1, $rs2, $imm5", []>,
Sched<[]>;
def CV_ADDRN : RVInstAlu_rri<0b00, 0b110, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
def CV_ADDRN : RVInstAlu_rri<0b10, 0b010, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
"cv.addrn", "$rd, $rs1, $rs2, $imm5", []>,
Sched<[]>;
def CV_ADDURN : RVInstAlu_rri<0b10, 0b110, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
def CV_ADDURN : RVInstAlu_rri<0b11, 0b010, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
"cv.addurn", "$rd, $rs1, $rs2, $imm5", []>,
Sched<[]>;
def CV_SUBN : RVInstAlu_rri<0b00, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
"cv.subn", "$rd, $rs1, $rs2, $imm5", []>,
Sched<[]>;
def CV_SUBUN : RVInstAlu_rri<0b10, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
def CV_SUBUN : RVInstAlu_rri<0b01, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
"cv.subun", "$rd, $rs1, $rs2, $imm5", []>,
Sched<[]>;
def CV_SUBRN : RVInstAlu_rri<0b00, 0b111, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
def CV_SUBRN : RVInstAlu_rri<0b10, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
"cv.subrn", "$rd, $rs1, $rs2, $imm5", []>,
Sched<[]>;
def CV_SUBURN : RVInstAlu_rri<0b10, 0b111, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
def CV_SUBURN : RVInstAlu_rri<0b11, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
"cv.suburn", "$rd, $rs1, $rs2, $imm5", []>,
Sched<[]>;
} // Predicates = [HasExtXCoreVAlu], hasSideEffects = 0, mayLoad = 0, mayStore = 0

let Predicates = [HasExtXCoreVAlu], hasSideEffects = 0, mayLoad = 0, mayStore = 0, Opcode = OPC_CUSTOM2.Value, Constraints = "$rd = $rd_wb" in {
def CV_ADDNR : RVInstAlu_rr<0b0100000, 0b010, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
let Predicates = [HasExtXCoreVAlu], hasSideEffects = 0, mayLoad = 0, mayStore = 0, Opcode = OPC_CUSTOM1.Value, Constraints = "$rd = $rd_wb" in {
def CV_ADDNR : RVInstAlu_rr<0b1000000, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
"cv.addnr", "$rd, $rs1, $rs2", []>,
Sched<[]>;
def CV_ADDUNR : RVInstAlu_rr<0b1100000, 0b010, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
def CV_ADDUNR : RVInstAlu_rr<0b1000001, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
"cv.addunr", "$rd, $rs1, $rs2", []>,
Sched<[]>;
def CV_ADDRNR : RVInstAlu_rr<0b0100000, 0b110, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
def CV_ADDRNR : RVInstAlu_rr<0b1000010, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
"cv.addrnr", "$rd, $rs1, $rs2", []>,
Sched<[]>;
def CV_ADDURNR : RVInstAlu_rr<0b1100000, 0b110, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
def CV_ADDURNR : RVInstAlu_rr<0b1000011, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
"cv.addurnr", "$rd, $rs1, $rs2", []>,
Sched<[]>;
def CV_SUBNR : RVInstAlu_rr<0b0100000, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
def CV_SUBNR : RVInstAlu_rr<0b1000100, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
"cv.subnr", "$rd, $rs1, $rs2", []>,
Sched<[]>;
def CV_SUBUNR : RVInstAlu_rr<0b1100000, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
def CV_SUBUNR : RVInstAlu_rr<0b1000101, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
"cv.subunr", "$rd, $rs1, $rs2", []>,
Sched<[]>;
def CV_SUBRNR : RVInstAlu_rr<0b0100000, 0b111, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
def CV_SUBRNR : RVInstAlu_rr<0b1000110, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
"cv.subrnr", "$rd, $rs1, $rs2", []>,
Sched<[]>;
def CV_SUBURNR : RVInstAlu_rr<0b1100000, 0b111, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
def CV_SUBURNR : RVInstAlu_rr<0b1000111, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
"cv.suburnr", "$rd, $rs1, $rs2", []>,
Sched<[]>;

} // Predicates = [HasExtXCoreVAlu], hasSideEffects = 0, mayLoad = 0, mayStore = 0, Opcode = OPC_CUSTOM2.Value, Constraints = "$rd = $rd_wb"
} // Predicates = [HasExtXCoreVAlu], hasSideEffects = 0, mayLoad = 0, mayStore = 0, Opcode = OPC_CUSTOM1.Value, Constraints = "$rd = $rd_wb"

let Predicates = [HasExtXCoreVAlu], hasSideEffects = 0, mayLoad = 0, mayStore = 0, isBranch = 1, isTerminator = 1 in {
// Immediate branching operations
Expand Down
62 changes: 31 additions & 31 deletions llvm/test/MC/RISCV/corev/alu-all-extensions.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,129 +5,129 @@

cv.abs t0, t1
# CHECK-INSTR: cv.abs t0, t1
# CHECK-ENCODING: [0xb3,0x02,0x03,0x04]
# CHECK-ENCODING: [0xab,0x32,0x03,0x50]

cv.slet t0, t1, t2
# CHECK-INSTR: cv.slet t0, t1, t2
# CHECK-ENCODING: [0xb3,0x22,0x73,0x04]
# CHECK-ENCODING: [0xab,0x32,0x73,0x52]

cv.sletu t0, t1, t2
# CHECK-INSTR: cv.sletu t0, t1, t2
# CHECK-ENCODING: [0xb3,0x32,0x73,0x04]
# CHECK-ENCODING: [0xab,0x32,0x73,0x54]

cv.min t0, t1, t2
# CHECK-INSTR: cv.min t0, t1, t2
# CHECK-ENCODING: [0xb3,0x42,0x73,0x04]
# CHECK-ENCODING: [0xab,0x32,0x73,0x56]

cv.minu t0, t1, t2
# CHECK-INSTR: cv.minu t0, t1, t2
# CHECK-ENCODING: [0xb3,0x52,0x73,0x04]
# CHECK-ENCODING: [0xab,0x32,0x73,0x58]

cv.max t0, t1, t2
# CHECK-INSTR: cv.max t0, t1, t2
# CHECK-ENCODING: [0xb3,0x62,0x73,0x04]
# CHECK-ENCODING: [0xab,0x32,0x73,0x5a]

cv.maxu t0, t1, t2
# CHECK-INSTR: cv.maxu t0, t1, t2
# CHECK-ENCODING: [0xb3,0x72,0x73,0x04]
# CHECK-ENCODING: [0xab,0x32,0x73,0x5c]

cv.exths t0, t1
# CHECK-INSTR: cv.exths t0, t1
# CHECK-ENCODING: [0xb3,0x42,0x03,0x10]
# CHECK-ENCODING: [0xab,0x32,0x03,0x5e]

cv.exthz t0, t1
# CHECK-INSTR: cv.exthz t0, t1
# CHECK-ENCODING: [0xb3,0x52,0x03,0x10]
# CHECK-ENCODING: [0xab,0x32,0x03,0x60]

cv.extbs t0, t1
# CHECK-INSTR: cv.extbs t0, t1
# CHECK-ENCODING: [0xb3,0x62,0x03,0x10]
# CHECK-ENCODING: [0xab,0x32,0x03,0x62]

cv.extbz t0, t1
# CHECK-INSTR: cv.extbz t0, t1
# CHECK-ENCODING: [0xb3,0x72,0x03,0x10]
# CHECK-ENCODING: [0xab,0x32,0x03,0x64]


cv.clip t0, t1, 5
# CHECK-INSTR: cv.clip t0, t1, 5
# CHECK-ENCODING: [0xb3,0x12,0x53,0x14]
# CHECK-ENCODING: [0xab,0x32,0x53,0x70]

cv.clipu t0, t1, 5
# CHECK-INSTR: cv.clipu t0, t1, 5
# CHECK-ENCODING: [0xb3,0x22,0x53,0x14]
# CHECK-ENCODING: [0xab,0x32,0x53,0x72]

cv.clipr t0, t1, t2
# CHECK-INSTR: cv.clipr t0, t1, t2
# CHECK-ENCODING: [0xb3,0x52,0x73,0x14]
# CHECK-ENCODING: [0xab,0x32,0x73,0x74]

cv.clipur t0, t1, t2
# CHECK-INSTR: cv.clipur t0, t1, t2
# CHECK-ENCODING: [0xb3,0x62,0x73,0x14]
# CHECK-ENCODING: [0xab,0x32,0x73,0x76]


cv.addn t0, t1, t2, 5
# CHECK-INSTR: cv.addn t0, t1, t2, 5
# CHECK-ENCODING: [0xdb,0x22,0x73,0x0a]
# CHECK-ENCODING: [0xab,0x22,0x73,0x0a]

cv.addun t0, t1, t2, 5
# CHECK-INSTR: cv.addun t0, t1, t2, 5
# CHECK-ENCODING: [0xdb,0x22,0x73,0x8a]
# CHECK-ENCODING: [0xab,0x22,0x73,0x4a]

cv.addrn t0, t1, t2, 5
# CHECK-INSTR: cv.addrn t0, t1, t2, 5
# CHECK-ENCODING: [0xdb,0x62,0x73,0x0a]
# CHECK-ENCODING: [0xab,0x22,0x73,0x8a]

cv.addurn t0, t1, t2, 5
# CHECK-INSTR: cv.addurn t0, t1, t2, 5
# CHECK-ENCODING: [0xdb,0x62,0x73,0x8a]
# CHECK-ENCODING: [0xab,0x22,0x73,0xca]

cv.subn t0, t1, t2, 5
# CHECK-INSTR: cv.subn t0, t1, t2, 5
# CHECK-ENCODING: [0xdb,0x32,0x73,0x0a]
# CHECK-ENCODING: [0xab,0x32,0x73,0x0a]

cv.subun t0, t1, t2, 5
# CHECK-INSTR: cv.subun t0, t1, t2, 5
# CHECK-ENCODING: [0xdb,0x32,0x73,0x8a]
# CHECK-ENCODING: [0xab,0x32,0x73,0x4a]

cv.subrn t0, t1, t2, 5
# CHECK-INSTR: cv.subrn t0, t1, t2, 5
# CHECK-ENCODING: [0xdb,0x72,0x73,0x0a]
# CHECK-ENCODING: [0xab,0x32,0x73,0x8a]

cv.suburn t0, t1, t2, 5
# CHECK-INSTR: cv.suburn t0, t1, t2, 5
# CHECK-ENCODING: [0xdb,0x72,0x73,0x8a]
# CHECK-ENCODING: [0xab,0x32,0x73,0xca]

cv.addnr t0, t1, t2
# CHECK-INSTR: cv.addnr t0, t1, t2
# CHECK-ENCODING: [0xdb,0x22,0x73,0x40]
# CHECK-ENCODING: [0xab,0x32,0x73,0x80]

cv.addunr t0, t1, t2
# CHECK-INSTR: cv.addunr t0, t1, t2
# CHECK-ENCODING: [0xdb,0x22,0x73,0xc0]
# CHECK-ENCODING: [0xab,0x32,0x73,0x82]

cv.addrnr t0, t1, t2
# CHECK-INSTR: cv.addrnr t0, t1, t2
# CHECK-ENCODING: [0xdb,0x62,0x73,0x40]
# CHECK-ENCODING: [0xab,0x32,0x73,0x84]

cv.addurnr t0, t1, t2
# CHECK-INSTR: cv.addurnr t0, t1, t2
# CHECK-ENCODING: [0xdb,0x62,0x73,0xc0]
# CHECK-ENCODING: [0xab,0x32,0x73,0x86]

cv.subnr t0, t1, t2
# CHECK-INSTR: cv.subnr t0, t1, t2
# CHECK-ENCODING: [0xdb,0x32,0x73,0x40]
# CHECK-ENCODING: [0xab,0x32,0x73,0x88]

cv.subunr t0, t1, t2
# CHECK-INSTR: cv.subunr t0, t1, t2
# CHECK-ENCODING: [0xdb,0x32,0x73,0xc0]
# CHECK-ENCODING: [0xab,0x32,0x73,0x8a]

cv.subrnr t0, t1, t2
# CHECK-INSTR: cv.subrnr t0, t1, t2
# CHECK-ENCODING: [0xdb,0x72,0x73,0x40]
# CHECK-ENCODING: [0xab,0x32,0x73,0x8c]

cv.suburnr t0, t1, t2
# CHECK-INSTR: cv.suburnr t0, t1, t2
# CHECK-ENCODING: [0xdb,0x72,0x73,0xc0]
# CHECK-ENCODING: [0xab,0x32,0x73,0x8e]


cv.beqimm t0, 0, 0
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/MC/RISCV/corev/alu/abs.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,8 @@

cv.abs t0, t1
# CHECK-INSTR: cv.abs t0, t1
# CHECK-ENCODING: [0xb3,0x02,0x03,0x04]
# CHECK-ENCODING: [0xab,0x32,0x03,0x50]

cv.abs a0, a1
# CHECK-INSTR: cv.abs a0, a1
# CHECK-ENCODING: [0x33,0x85,0x05,0x04]
# CHECK-ENCODING: [0x2b,0xb5,0x05,0x50]
6 changes: 3 additions & 3 deletions llvm/test/MC/RISCV/corev/alu/addn.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,12 +3,12 @@

cv.addn t0, t1, t2, 0
# CHECK-INSTR: cv.addn t0, t1, t2, 0
# CHECK-ENCODING: [0xdb,0x22,0x73,0x00]
# CHECK-ENCODING: [0xab,0x22,0x73,0x00]

cv.addn t0, t1, t2, 16
# CHECK-INSTR: cv.addn t0, t1, t2, 16
# CHECK-ENCODING: [0xdb,0x22,0x73,0x20]
# CHECK-ENCODING: [0xab,0x22,0x73,0x20]

cv.addn a0, a1, zero, 31
# CHECK-INSTR: cv.addn a0, a1, zero, 31
# CHECK-ENCODING: [0x5b,0xa5,0x05,0x3e]
# CHECK-ENCODING: [0x2b,0xa5,0x05,0x3e]
4 changes: 2 additions & 2 deletions llvm/test/MC/RISCV/corev/alu/addnr.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,8 @@

cv.addnr t0, t1, t2
# CHECK-INSTR: cv.addnr t0, t1, t2
# CHECK-ENCODING: [0xdb,0x22,0x73,0x40]
# CHECK-ENCODING: [0xab,0x32,0x73,0x80]

cv.addnr a0, a1, a2
# CHECK-INSTR: cv.addnr a0, a1, a2
# CHECK-ENCODING: [0x5b,0xa5,0xc5,0x40]
# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x80]
6 changes: 3 additions & 3 deletions llvm/test/MC/RISCV/corev/alu/addrn.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,12 +3,12 @@

cv.addrn t0, t1, t2, 0
# CHECK-INSTR: cv.addrn t0, t1, t2, 0
# CHECK-ENCODING: [0xdb,0x62,0x73,0x00]
# CHECK-ENCODING: [0xab,0x22,0x73,0x80]

cv.addrn t0, t1, t2, 16
# CHECK-INSTR: cv.addrn t0, t1, t2, 16
# CHECK-ENCODING: [0xdb,0x62,0x73,0x20]
# CHECK-ENCODING: [0xab,0x22,0x73,0xa0]

cv.addrn a0, a1, zero, 31
# CHECK-INSTR: cv.addrn a0, a1, zero, 31
# CHECK-ENCODING: [0x5b,0xe5,0x05,0x3e]
# CHECK-ENCODING: [0x2b,0xa5,0x05,0xbe]
4 changes: 2 additions & 2 deletions llvm/test/MC/RISCV/corev/alu/addrnr.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,8 @@

cv.addrnr t0, t1, t2
# CHECK-INSTR: cv.addrnr t0, t1, t2
# CHECK-ENCODING: [0xdb,0x62,0x73,0x40]
# CHECK-ENCODING: [0xab,0x32,0x73,0x84]

cv.addrnr a0, a1, a2
# CHECK-INSTR: cv.addrnr a0, a1, a2
# CHECK-ENCODING: [0x5b,0xe5,0xc5,0x40]
# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x84]
Loading

0 comments on commit ad21787

Please sign in to comment.