🐛 Stall pipeline in write-after-write loads

Fixes #8 by making sure that newer instructions cannot be overtaken by an in-flight stalled load.
openhwgroup · Dec 20, 2017 · f9354dc · f9354dc
1 parent c5f1a3a
commit f9354dc
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Showing 2 changed files with 9 additions and 1 deletion.
diff --git a/riscv_controller.sv b/riscv_controller.sv
@@ -118,8 +118,12 @@ module riscv_controller
   input  logic [DBG_SETS_W-1:0] dbg_settings_i,
   output logic        dbg_trap_o,
 
+  // Regfile target
+  input  logic [5:0]  regfile_alu_waddr_id_i,     // currently decoded target address
+
   // Forwarding signals from regfile
   input  logic        regfile_we_ex_i,            // FW: write enable from  EX stage
+  input  logic [5:0]  regfile_waddr_ex_i,         // FW: write address from EX stage
   input  logic        regfile_we_wb_i,            // FW: write enable from  WB stage
   input  logic        regfile_alu_we_fw_i,        // FW: ALU/MUL write enable from  EX stage
 
@@ -726,7 +730,7 @@ module riscv_controller
           ( (data_req_ex_i == 1'b1) && (regfile_we_ex_i == 1'b1) ||
            (wb_ready_i == 1'b0) && (regfile_we_wb_i == 1'b1)
           ) &&
-          ( (reg_d_ex_is_reg_a_i == 1'b1) || (reg_d_ex_is_reg_b_i == 1'b1) || (reg_d_ex_is_reg_c_i == 1'b1) )
+          ( (reg_d_ex_is_reg_a_i == 1'b1) || (reg_d_ex_is_reg_b_i == 1'b1) || (reg_d_ex_is_reg_c_i == 1'b1) || (regfile_waddr_ex_i == regfile_alu_waddr_id_i))
        )
     begin
       deassert_we_o   = 1'b1;

diff --git a/riscv_id_stage.sv b/riscv_id_stage.sv
@@ -1169,8 +1169,12 @@ module riscv_id_stage
     .dbg_settings_i                 ( dbg_settings_i         ),
     .dbg_trap_o                     ( dbg_trap_o             ),
 
+    // Write targets from ID
+    .regfile_alu_waddr_id_i         ( regfile_alu_waddr_id   ),
+
     // Forwarding signals from regfile
     .regfile_we_ex_i                ( regfile_we_ex_o        ),
+    .regfile_waddr_ex_i             ( regfile_waddr_ex_o     ),
     .regfile_we_wb_i                ( regfile_we_wb_i        ),
 
     // regfile port 2