regfile_we_wb set from wb_ready_i caused load_stall to occur one instruction too late.

[mcockrell-google]

In the controller the pending load is indicated by WB not ready and regfile_we_wg high. This occurs one cycle too late in successive loads. Keeping the prior logic of setting regfile_we_wb high when the regifle_we_lsu is high accurately indicates a pending load and wb in the correct cycle.

[davideschiavone]

Hello Matt, thanks for reporting it.

Can you provide please an example and/or waveforms so that we can try to reproduce and fix the bug?

Thanks a lot
Davide

[mcockrell-google]

Hi Davide - [image: image.png] See the above screen shot of the trace log. There is a lbu instruction executed (PC = b560). The branch is executed with the wrong value loaded in x10. (see screenshot below) As you can see the read stall for the load from 2392d occurs a cycle late. [image: image.png] [image: image.png] Let me know if you need any more information. Matt

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On Wed, Apr 25, 2018 at 4:38 AM Pasquale Davide Schiavone < ***@***.***> wrote: Hello Matt, thanks for reporting it. Can you provide please an example and/or waveforms so that we can try to reproduce and fix the bug? Thanks a lot Davide — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub <#37 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AcaER3ZjsHaa_0bgSuTkE4cZZGXgObRmks5tsGAxgaJpZM4TcFhv> .

[davideschiavone]

Hi Matt, thanks a lot but I can't see the images, maybe it is easier if you send them to me by email.

Thanks a lot
Best
Davide

[davideschiavone]

Solved here: 3606a02