Merge pull request #510 from silabs-oysteink/silabs-oysteink_mstateen…

…0-flush-UM Updated cycle count for CSR instructions accessing mstateen0.
openhwgroup · Sep 20, 2023 · 69f2cc0 · 69f2cc0
2 parents 0087020 + 0f690a5
commit 69f2cc0
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/docs/user_manual/source/pipeline.rst b/docs/user_manual/source/pipeline.rst
@@ -42,7 +42,8 @@ and zero stall on the data-side memory interface.
   |                       |                                      | RISCV-V RV32I Base Integer Instruction Set.                 |
   +-----------------------+--------------------------------------+-------------------------------------------------------------+
   | CSR Access            | 4 (``jvt``, ``cpuctrl``, ``pmp*``    | CSR Access Instruction are defined in 'Zicsr' of the        |
-  |                       |    ``secureseed*``, ``mseccfg``)     |                                                             |
+  |                       |    ``secureseed*``, ``mseccfg``,     |                                                             |
+  |                       |    ``mstateen0``                     |                                                             |
   |                       |                                      | RISC-V specification.                                       |
   |                       | 1 (all the other CSRs)               |                                                             |
   +-----------------------+--------------------------------------+-------------------------------------------------------------+