Fix issues after merge

Signed-off-by: Oivind Ekelund <oivind.ekelund@silabs.com>
openhwgroup · May 16, 2023 · fbbbc57 · fbbbc57
1 parent 8145f53
commit fbbbc57
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Showing 3 changed files with 3 additions and 5 deletions.
diff --git a/rtl/cv32e40s_controller_bypass.sv b/rtl/cv32e40s_controller_bypass.sv
@@ -203,10 +203,6 @@ module cv32e40s_controller_bypass import cv32e40s_pkg::*;
                             ((id_ex_pipe_i.alu_jmp && id_ex_pipe_i.alu_en && !id_ex_pipe_i.last_sec_op && id_ex_pipe_i.instr_valid));
 
 
-  // Stall ID when WFI or WFE is active in EX.
-  // Prevent load/store following a WFI or WFE in the pipeline
-  assign ctrl_byp_o.wfi_wfe_stall = (id_ex_pipe_i.sys_en && (id_ex_pipe_i.sys_wfi_insn || id_ex_pipe_i.sys_wfe_insn) && id_ex_pipe_i.instr_valid);
-
   // Stall ID when instruction that can trigger sleep (e.g. WFI or WFE) is active in EX.
   // Prevent load/store following a sleep instruction in the pipeline
   assign ctrl_byp_o.sleep_stall = (id_ex_pipe_i.sys_en && (id_ex_pipe_i.sys_wfi_insn || id_ex_pipe_i.sys_wfe_insn) && id_ex_pipe_i.instr_valid);

diff --git a/sva/cv32e40s_controller_fsm_sva.sv b/sva/cv32e40s_controller_fsm_sva.sv
@@ -369,7 +369,7 @@ module cv32e40s_controller_fsm_sva
     assert property (@(posedge clk) disable iff (!rst_n)
                       // Disregard higher priority exceptions and trigger match, and debug as WFI masked during debug
                       !(((ex_wb_pipe_i.instr.mpu_status != MPU_OK) || ex_wb_pipe_i.instr.bus_resp.err || trigger_match_in_wb) && ex_wb_pipe_i.instr_valid) &&
-                      !ctrl_fsm_o.debug_wfi_wfe_no_sleep &&
+                      !ctrl_fsm_o.debug_no_sleep &&
                       // Check for wfi in instruction word and user mode
                       ((ex_wb_pipe_i.instr.bus_resp.rdata == 32'h10500073) && ex_wb_pipe_i.instr_valid && (priv_lvl_i == PRIV_LVL_U) && !mstatus_i.tw)
                       |-> (!exception_in_wb && (ex_wb_pipe_i.sys_en && ex_wb_pipe_i.sys_wfi_insn)))

diff --git a/sva/cv32e40s_id_stage_sva.sv b/sva/cv32e40s_id_stage_sva.sv
@@ -45,6 +45,7 @@ module cv32e40s_id_stage_sva
   input alu_op_a_mux_e  alu_op_a_mux_sel,
   input alu_op_b_mux_e  alu_op_b_mux_sel,
   input op_c_mux_e      op_c_mux_sel,
+  input logic           sys_mret_insn,
   input logic           ex_ready_i,
   input logic           illegal_insn,
   input logic [31:0]    operand_a_fw,
@@ -53,6 +54,7 @@ module cv32e40s_id_stage_sva
   input rf_addr_t       rf_raddr_o[REGFILE_NUM_READ_PORTS],
   input rf_data_t       rf_rdata_i[REGFILE_NUM_READ_PORTS],
   input csr_opcode_e    csr_op,
+  input if_id_pipe_t    if_id_pipe_i,
   input id_ex_pipe_t    id_ex_pipe_o,
   input ex_wb_pipe_t    ex_wb_pipe,
   input logic           id_ready_o,