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ISS flags a mismatch after reading the DCSR cause field.
The error happens in a GPR a cycle after the DCSR is read because DCSR checks have been temporarily turned off.
Steps to Reproduce
Hash: 723c1ba
Note: Comment out a_dcsr_cause and a_debug_mode_ext_req assertions as they are not ye updated for current RTL
cmd: makeuvmt gen_corev-dv corev-dv gen_comp comp test TEST=corev_rand_debug
When waking up from sleep (exiting FSM state SLEEP), the cause of wakeup is now flopped to enable the FSM to take the action according to the wakeup reason, although there may be higher priority events appearing after the wakeup.
Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
ISS flags a mismatch after reading the DCSR cause field.
The error happens in a GPR a cycle after the DCSR is read because DCSR checks have been temporarily turned off.
Steps to Reproduce
Hash: 723c1ba
Note: Comment out a_dcsr_cause and a_debug_mode_ext_req assertions as they are not ye updated for current RTL
cmd: makeuvmt gen_corev-dv corev-dv gen_comp comp test TEST=corev_rand_debug
Log :
UVM_INFO @ 114.300 ns : uvmt_cv32e40s_firmware_test.sv(143) uvm_test_top [TEST] Started RUN
Error (IDV) GPR register value mismatch (HartId:0, PC:1a110878):
Info (IDV) 0> GPR x7 - dut:400084d3 ref:40008453
UVM_ERROR @ 318847.300 ns : rvvi-pkg.sv(94) reporter [] uvmt_cv32e40s_tb.imperas_dv.trace2api.state_compare @ 318847.000 ns: MISMATCH
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