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Wrong clearing of bits in pmp_addr_q #388

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silabs-oysteink opened this issue Jan 12, 2023 · 3 comments
Closed

Wrong clearing of bits in pmp_addr_q #388

silabs-oysteink opened this issue Jan 12, 2023 · 3 comments
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@silabs-oivind
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Status:Resolved Issue has been resolved, but closure is pending on git merge and/or issuer confirmation

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@silabs-oysteink
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silabs-oysteink commented Jan 12, 2023 •
edited

Wrong clearing of bits in pmp_addr_q

Component

Component:RTL: For issues in the RTL (e.g. for files in the rtl directory)

Steps to Reproduce

  1. RTL hash 5a0df34
  2. Running formal verification, the assertion "a_set_clear_pmp_addr_q" within cv32e40s_cs_registers_sva.sv should fail.

When granularity >=1 and the mode is either OFF or TOR, the read data resolution will tie off the least significant implemented (flipflop) bit to 0. This may propagate back through the RMW operation and inadvertently clear the flipflop when it shouldn't.
@silabs-oysteink
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This is actually in reality a duplicate of issue #302. Keeping it separate as it is very PMP specific. When fixed, both this issue and #302 may likely be closed.

silabs-oivind added a commit to silabs-oivind/cv32e40s that referenced this issue Mar 24, 2023
@silabs-oivind
Fix for issue openhwgroup#388
3abc63e 
Signed-off-by: Oivind Ekelund <oivind.ekelund@silabs.com>
Silabs-ArjanB added a commit that referenced this issue Apr 12, 2023
@Silabs-ArjanB
Merge pull request #425 from silabs-oivind/fix_issue_388
66436bf 
Fix for issue #388
@Silabs-ArjanB Silabs-ArjanB added the Status:Resolved Issue has been resolved, but closure is pending on git merge and/or issuer confirmation label Apr 12, 2023
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@silabs-oysteink Can this issue and #302 both be (fully) closed now?

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Yes, I will close them.

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