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RVFI misrepresents OBI transactions? #410

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silabs-robin opened this issue Feb 27, 2023 · 5 comments
Closed

RVFI misrepresents OBI transactions? #410

silabs-robin opened this issue Feb 27, 2023 · 5 comments
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Component:Other Non-RTL, non-documentation (e.g. bhv, sva) Status:Resolved Issue has been resolved, but closure is pending on git merge and/or issuer confirmation Type:Bug For bugs in any content (RTL, Documentation, etc.)

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@silabs-robin
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Component

Component:Other: For any other issues

Steps to Reproduce

  1. Cvverif hash f7f2d5
  2. My fork https://github.com/silabs-robin/core-v-verif
  3. tcf_cvverif
  4. a_obi_vs_rvfi

If I there is nothing I have overlooked, it seems like rvfi_mem_* reports memory writes that didn't happen.
In the example below it seems like there is an MPU error, so the bus access is denied, but RVFI says the mem got updated.

image

@Silabs-ArjanB Silabs-ArjanB added Component:Other Non-RTL, non-documentation (e.g. bhv, sva) Type:Bug For bugs in any content (RTL, Documentation, etc.) labels Feb 27, 2023
@Silabs-ArjanB
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It looks like an RVFI bug indeed (it ignores the related valid signal and acts as if a memory write actually happened).

@silabs-robin I would assume that rvfi_trap.trap gets asserted as well, right?

@silabs-robin
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I would assume that rvfi_trap.trap gets asserted as well, right?

Yes.

image

@Silabs-ArjanB
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Should be fixed by openhwgroup/cv32e40x#816 (once merged from 40X to 40S)

@Silabs-ArjanB Silabs-ArjanB added the Status:Resolved Issue has been resolved, but closure is pending on git merge and/or issuer confirmation label Mar 27, 2023
silabs-oysteink added a commit to silabs-oysteink/cv32e40s that referenced this issue Mar 29, 2023
…y went into the write buffer (not blocked by WPT, MPU or alignment checker).

Fixes issue openhwgroup#410 on cv32e40s.

Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
silabs-oysteink pushed a commit to silabs-oysteink/cv32e40s that referenced this issue Mar 29, 2023
@silabs-oysteink
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@silabs-robin Issue should now be resolved, can you check and close if you can confirm?

@silabs-robin
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I am seeing a bound of more than double where the original CEX was found, and we have reports of a bound of "26 cycles / 12k seconds ".
Therefore, I consider the problem fixed.

(If there exists any further problem on deeper depths then I will create a new issue for that separately.)

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Labels
Component:Other Non-RTL, non-documentation (e.g. bhv, sva) Status:Resolved Issue has been resolved, but closure is pending on git merge and/or issuer confirmation Type:Bug For bugs in any content (RTL, Documentation, etc.)
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