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Merge from CV32E40X #485
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Silabs-ArjanB
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openhwgroup:master
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silabs-oysteink:silabs-oysteink_merge-w34-1
Aug 28, 2023
Merged
Merge from CV32E40X #485
Silabs-ArjanB
merged 26 commits into
openhwgroup:master
from
silabs-oysteink:silabs-oysteink_merge-w34-1
Aug 28, 2023
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… EX stage. Routing halt_ex and kill_ex into the multiplier and divider, making sure no state updates occur while halted and that the modules properly drive valid/ready according to halt/kill. SEC clean (multiplier operation was converted to addition to be able to complete SEC run) Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
SEC clean. Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
…fter/in parallell with the case. Clock gating flipflops when halted or when there are no valid inputs. SEC clean (with multiplier operation modified to addition) Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
…eink/cv32e40x into silabs-oysteink-div-mul-todo
Signed-off-by: Arjan Bink <Arjan.Bink@silabs.com>
Signed-off-by: Arjan Bink <Arjan.Bink@silabs.com>
Updated RISC-V debug spec to version of June 23 2023
Added statement that wu_wfe_i is positive level sensitive
Signed-off-by: Arjan Bink <Arjan.Bink@silabs.com>
Updated RISC-V CLIC version to 8/1/2023 version
Explicit build.os is now required by RTD.
Update .readthedocs.yaml
Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
Checked with a temporary assertion for correctness. Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
…-xif Fix for issue #882
Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
Fix for issue #892
…ceptions and Interrupts" chapter in the user manual. Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
Fix for issue #881
Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
…todo Fixed todo's related to mul_en/div_en i EX stage
…k_merge-w34-1 Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
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Aug 28, 2023
The external CLIC module prioritizes all interrupts and presents |corev| with the highest priority pending and enabled interrupt. | ||
|corev| will then prioritize the interrupts including NMI as follows: | ||
|
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* ``store bus fault NMI (1025)`` |
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Add codes 1026, 1027
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Added codes.
Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
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SEC clean (with multiplier operation temporarily converted to an add)