Changed logic for sequence progress detection #638
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…B and ID by using flipflops, and the SVA part uses the old combinatorial method. Done to avoid combinatorial loops in future cleanup. SEC is undetermined at the point of commit. Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
Silabs-ArjanB
added
the
Component:RTL
bhv/cv32e40x_wrapper.sv
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| .first_op_if_i (core_i.first_op_if), | ||
| .first_op_ex_i (core_i.first_op_ex), | ||
| .instr_valid_if_i (core_i.if_stage_i.prefetch_valid), | ||
| .ptr_in_if_i (core_i.if_stage_i.prefetch_is_tbljmp_ptr), |
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No signal renaming like this in connections, especially because ptr_in_if seems to imply both table jump pointer and clic pointer
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I will fix it.
| logic id_stage_haltable; | ||
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| assign sequence_interruptible = !sequence_in_progress_wb; |
rtl/cv32e40x_controller_fsm.sv
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| sequence_in_progress_wb <= 1'b0; | ||
| end else begin | ||
| if (!sequence_in_progress_wb) begin | ||
| if (wb_valid_i && ex_wb_pipe_i.first_op && !last_op_wb_i) begin |
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I would expect this to also be qualified by ex_wb_pipe_i.instr_valid; shouldn't it?
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That should not be needed, as wb_valid_i already depends on ex_wb_pipe_i.instr_valid
| end | ||
| end else begin | ||
| // sequence_in_progress_wb is set, clear when last_op retires | ||
| if (wb_valid_i && last_op_wb_i) begin |
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Same reply as above
rtl/cv32e40x_controller_fsm.sv
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| end | ||
| end | ||
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| // Helper logic to track first_op and last_op through the ID stage to detect unhaltable sequences |
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Update comment; this is not 'helper logic'
| end | ||
| end else begin | ||
| // sequence_in_progress_id is set, clear when last_op retires | ||
| if (id_valid_i && ex_ready_i && last_op_id_i) begin |
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Same remarks as above related to usage of isntr_valid. Is adding the instr_valid signals a SEC clean change?
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It would likely be SEC clean, but as for the others the instr_valid is baked into the valid
Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
Swapped the RTL detection logic with the logic used in the SVA file. This is done to avoid a combinatorial loop is using 'seq_valid' to calculate first_op of the IF stage.
First PR of a series to clean up Zc code and in particular handling of first_op and last_op.
SEC not determined at the time of PR (for both ZC_EXT=0 and ZC_EXT=1)