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Updates due to updated debug spec #858

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merged 4 commits into from May 22, 2023
Merged

Updates due to updated debug spec #858

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15b88c8
Removed tdata3 and tcontrol.
silabs-oysteink May 12, 2023
f2b3433
Updated mcontrol6 to version 1.
silabs-oysteink May 22, 2023
cfb686f
Updated yaml file for debug:
silabs-oysteink May 22, 2023
f3f3636
Updates after review.
silabs-oysteink May 22, 2023
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38 changes: 7 additions & 31 deletions bhv/cv32e40x_rvfi.sv
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Expand Up @@ -109,7 +109,7 @@ module cv32e40x_rvfi
input logic csr_mscratchcsw_in_wb_i,
input logic csr_mscratchcswl_in_wb_i,
input logic csr_mnxti_in_wb_i,
input logic wpt_match_wb_i,
input logic [31:0] wpt_match_wb_i,
input mpu_status_e mpu_status_wb_i,
input align_status_e align_status_wb_i,

Expand Down Expand Up @@ -196,15 +196,9 @@ module cv32e40x_rvfi
input logic [31:0] csr_tdata2_n_i,
input logic [31:0] csr_tdata2_q_i,
input logic csr_tdata2_we_i,
input logic [31:0] csr_tdata3_n_i,
input logic [31:0] csr_tdata3_q_i,
input logic csr_tdata3_we_i,
input logic [31:0] csr_tinfo_n_i,
input logic [31:0] csr_tinfo_q_i,
input logic csr_tinfo_we_i,
input logic [31:0] csr_tcontrol_n_i,
input logic [31:0] csr_tcontrol_q_i,
input logic csr_tcontrol_we_i,
input logic [31:0] csr_tselect_n_i,
input logic [31:0] csr_tselect_q_i,
input logic csr_tselect_we_i,
Expand Down Expand Up @@ -426,18 +420,14 @@ module cv32e40x_rvfi
output logic [31:0] rvfi_csr_tselect_wmask,
output logic [31:0] rvfi_csr_tselect_rdata,
output logic [31:0] rvfi_csr_tselect_wdata,
output logic [ 3:0] [31:0] rvfi_csr_tdata_rmask, // 1-3 implemented
output logic [ 3:0] [31:0] rvfi_csr_tdata_wmask,
output logic [ 3:0] [31:0] rvfi_csr_tdata_rdata,
output logic [ 3:0] [31:0] rvfi_csr_tdata_wdata,
output logic [ 2:0] [31:0] rvfi_csr_tdata_rmask, // 1-2 implemented
output logic [ 2:0] [31:0] rvfi_csr_tdata_wmask,
output logic [ 2:0] [31:0] rvfi_csr_tdata_rdata,
output logic [ 2:0] [31:0] rvfi_csr_tdata_wdata,
output logic [31:0] rvfi_csr_tinfo_rmask,
output logic [31:0] rvfi_csr_tinfo_wmask,
output logic [31:0] rvfi_csr_tinfo_rdata,
output logic [31:0] rvfi_csr_tinfo_wdata,
output logic [31:0] rvfi_csr_tcontrol_rmask,
output logic [31:0] rvfi_csr_tcontrol_wmask,
output logic [31:0] rvfi_csr_tcontrol_rdata,
output logic [31:0] rvfi_csr_tcontrol_wdata,
output logic [31:0] rvfi_csr_dcsr_rmask,
output logic [31:0] rvfi_csr_dcsr_wmask,
output logic [31:0] rvfi_csr_dcsr_rdata,
Expand Down Expand Up @@ -837,7 +827,7 @@ module cv32e40x_rvfi

// Indicate that a data transfer was blocked before reaching the bus.
logic mem_access_blocked_wb;
assign mem_access_blocked_wb = wpt_match_wb_i ||
assign mem_access_blocked_wb = |wpt_match_wb_i ||
(mpu_status_wb_i != MPU_OK) ||
(align_status_wb_i != ALIGN_OK);

Expand Down Expand Up @@ -1548,21 +1538,11 @@ module cv32e40x_rvfi
assign rvfi_csr_wdata_d.tdata[2] = csr_tdata2_n_i;
assign rvfi_csr_wmask_d.tdata[2] = csr_tdata2_we_i ? '1 : '0;

assign rvfi_csr_rdata_d.tdata[3] = csr_tdata3_q_i;
assign rvfi_csr_rmask_d.tdata[3] = '1;
assign rvfi_csr_wdata_d.tdata[3] = csr_tdata3_n_i;
assign rvfi_csr_wmask_d.tdata[3] = csr_tdata3_we_i ? '1 : '0;

assign rvfi_csr_rdata_d.tinfo = csr_tinfo_q_i;
assign rvfi_csr_rmask_d.tinfo = '1;
assign rvfi_csr_wdata_d.tinfo = csr_tinfo_n_i;
assign rvfi_csr_wmask_d.tinfo = csr_tinfo_we_i ? '1 : '0;

assign rvfi_csr_rdata_d.tcontrol = csr_tcontrol_q_i;
assign rvfi_csr_rmask_d.tcontrol = '1;
assign rvfi_csr_wdata_d.tcontrol = csr_tcontrol_n_i;
assign rvfi_csr_wmask_d.tcontrol = csr_tcontrol_we_i ? '1 : '0;

// Debug / Trace
assign ex_csr_rdata_d.nmip = csr_dcsr_q_i[3]; // dcsr.nmip is autonomous. Propagate read value from EX stage
assign rvfi_csr_rdata_d.dcsr = {csr_dcsr_q_i[31:4], ex_csr_rdata.nmip, csr_dcsr_q_i[2:0]};
Expand Down Expand Up @@ -1902,17 +1882,13 @@ module cv32e40x_rvfi
assign rvfi_csr_tselect_wmask = rvfi_csr_wmask.tselect;
assign rvfi_csr_tdata_rdata = rvfi_csr_rdata.tdata;
assign rvfi_csr_tdata_rmask[0] = '0; // Does not exist
assign rvfi_csr_tdata_rmask[3:1] = rvfi_csr_rmask.tdata[3:1];
assign rvfi_csr_tdata_rmask[2:1] = rvfi_csr_rmask.tdata[2:1];
assign rvfi_csr_tdata_wdata = rvfi_csr_wdata.tdata;
assign rvfi_csr_tdata_wmask = rvfi_csr_wmask.tdata;
assign rvfi_csr_tinfo_rdata = rvfi_csr_rdata.tinfo;
assign rvfi_csr_tinfo_rmask = rvfi_csr_rmask.tinfo;
assign rvfi_csr_tinfo_wdata = rvfi_csr_wdata.tinfo;
assign rvfi_csr_tinfo_wmask = rvfi_csr_wmask.tinfo;
assign rvfi_csr_tcontrol_rdata = rvfi_csr_rdata.tcontrol;
assign rvfi_csr_tcontrol_rmask = rvfi_csr_rmask.tcontrol;
assign rvfi_csr_tcontrol_wdata = rvfi_csr_wdata.tcontrol;
assign rvfi_csr_tcontrol_wmask = rvfi_csr_wmask.tcontrol;
assign rvfi_csr_dcsr_rdata = rvfi_csr_rdata.dcsr;
assign rvfi_csr_dcsr_rmask = rvfi_csr_rmask.dcsr;
assign rvfi_csr_dcsr_wdata = rvfi_csr_wdata.dcsr;
Expand Down
12 changes: 5 additions & 7 deletions bhv/cv32e40x_wrapper.sv
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Expand Up @@ -292,6 +292,9 @@ module cv32e40x_wrapper
.tdata1_q (core_i.cs_registers_i.debug_triggers_i.gen_triggers.tdata1_q),
.tdata2_q (core_i.cs_registers_i.debug_triggers_i.gen_triggers.tdata2_q),
.lsu_addr_match_en (core_i.cs_registers_i.debug_triggers_i.gen_triggers.lsu_addr_match_en),
.trigger_match_if_wb (core_i.ex_wb_pipe.trigger_match),
.trigger_match_ex_wb (core_i.wpt_match_wb),
.wb_valid_i (core_i.wb_valid),
.*);
end
endgenerate
Expand Down Expand Up @@ -328,7 +331,8 @@ module cv32e40x_wrapper
#(.A_EXT(A_EXT),
.DEBUG(DEBUG),
.PMA_NUM_REGIONS(PMA_NUM_REGIONS),
.CLIC(CLIC))
.CLIC(CLIC),
.DBG_NUM_TRIGGERS(DBG_NUM_TRIGGERS))
core_sva (// probed cs_registers signals
.cs_registers_mie_q (core_i.cs_registers_i.mie_q),
.cs_registers_mepc_n (core_i.cs_registers_i.mepc_n),
Expand Down Expand Up @@ -671,9 +675,6 @@ endgenerate
.csr_tdata2_n_i ( core_i.cs_registers_i.debug_triggers_i.tdata2_n_r ),
.csr_tdata2_q_i ( core_i.cs_registers_i.tdata2_rdata ),
.csr_tdata2_we_i ( core_i.cs_registers_i.debug_triggers_i.tdata2_we_r ),
.csr_tdata3_n_i ( core_i.cs_registers_i.debug_triggers_i.tdata3_n ),
.csr_tdata3_q_i ( core_i.cs_registers_i.tdata3_rdata ),
.csr_tdata3_we_i ( core_i.cs_registers_i.tdata3_we ),
.csr_tinfo_n_i ( core_i.cs_registers_i.debug_triggers_i.tinfo_n ),
.csr_tinfo_q_i ( core_i.cs_registers_i.tinfo_rdata ),
.csr_tinfo_we_i ( core_i.cs_registers_i.tinfo_we ),
Expand All @@ -700,9 +701,6 @@ endgenerate
.csr_mstatush_n_i ( core_i.cs_registers_i.mstatush_n ),
.csr_mstatush_q_i ( core_i.cs_registers_i.mstatush_rdata ),
.csr_mstatush_we_i ( core_i.cs_registers_i.mstatush_we ),
.csr_tcontrol_n_i ( core_i.cs_registers_i.debug_triggers_i.tcontrol_n ),
.csr_tcontrol_q_i ( core_i.cs_registers_i.tcontrol_rdata ),
.csr_tcontrol_we_i ( core_i.cs_registers_i.tcontrol_we ),
.csr_tselect_n_i ( core_i.cs_registers_i.debug_triggers_i.tselect_n ),
.csr_tselect_q_i ( core_i.cs_registers_i.tselect_rdata ),
.csr_tselect_we_i ( core_i.cs_registers_i.tselect_we ),
Expand Down
3 changes: 1 addition & 2 deletions bhv/include/cv32e40x_rvfi_pkg.sv
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Expand Up @@ -65,9 +65,8 @@ package cv32e40x_rvfi_pkg;
logic [31:0] mscratchcsw;
logic [31:0] mscratchcswl;
logic [31:0] tselect;
logic [ 3:0] [31:0] tdata;
logic [ 2:0] [31:0] tdata;
logic [31:0] tinfo;
logic [31:0] tcontrol;
logic [31:0] dcsr;
logic [31:0] dpc;
logic [ 1:0] [31:0] dscratch;
Expand Down
4 changes: 0 additions & 4 deletions bhv/include/cv32e40x_wrapper.vh
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Expand Up @@ -151,10 +151,6 @@
.rvfi_csr_tinfo_wmask(),\
.rvfi_csr_tinfo_rdata(),\
.rvfi_csr_tinfo_wdata(),\
.rvfi_csr_tcontrol_rmask(),\
.rvfi_csr_tcontrol_wmask(),\
.rvfi_csr_tcontrol_rdata(),\
.rvfi_csr_tcontrol_wdata(),\
.rvfi_csr_dcsr_rmask(),\
.rvfi_csr_dcsr_wmask(),\
.rvfi_csr_dcsr_rdata(),\
Expand Down
2 changes: 1 addition & 1 deletion rtl/cv32e40x_controller.sv
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Expand Up @@ -68,7 +68,7 @@ module cv32e40x_controller import cv32e40x_pkg::*;

input ex_wb_pipe_t ex_wb_pipe_i,
input mpu_status_e mpu_status_wb_i, // MPU status (WB stage)
input logic wpt_match_wb_i, // LSU watchpoint trigger in WB
input logic [31:0] wpt_match_wb_i, // LSU watchpoint trigger in WB
input align_status_e align_status_wb_i, // Aligned status (atomics and mret pointers) in WB

// Last operation bits
Expand Down
15 changes: 12 additions & 3 deletions rtl/cv32e40x_controller_fsm.sv
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Expand Up @@ -73,7 +73,7 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*;
input logic abort_op_wb_i, // WB stage contains an (to be) aborted instruction or sequence
input mpu_status_e mpu_status_wb_i, // MPU status (WB timing)
input align_status_e align_status_wb_i, // Aligned status (atomics) in WB
input logic wpt_match_wb_i, // LSU watchpoint trigger (WB)
input logic [31:0] wpt_match_wb_i, // LSU watchpoint trigger (WB)


// From LSU (WB)
Expand Down Expand Up @@ -178,7 +178,7 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*;
logic mret_ptr_in_wb; // CLIC pointer caused by mret is in WB
logic dret_in_wb;
logic ebreak_in_wb;
logic trigger_match_in_wb; // mcontrol6 trigger in WB
logic trigger_match_in_wb; // mcontrol2/6 trigger in WB
logic etrigger_in_wb; // exception trigger in WB
logic xif_in_wb;
logic clic_ptr_in_wb; // CLIC pointer caused by directly acking an SHV is in WB (no mret)
Expand Down Expand Up @@ -399,7 +399,7 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*;

// Trigger match in wb
// Trigger_match during debug mode is masked in the trigger logic inside cs_registers.sv
assign trigger_match_in_wb = ((ex_wb_pipe_i.trigger_match || wpt_match_wb_i) && ex_wb_pipe_i.instr_valid);
assign trigger_match_in_wb = ((|ex_wb_pipe_i.trigger_match) || (|wpt_match_wb_i)) && ex_wb_pipe_i.instr_valid;

// Only set the etrigger_in_wb flag when wb_valid is true (WB is not halted or killed).
// If a higher priority event than taking an exception (NMI, external debug or interrupts) are present, wb_valid_i will be
Expand Down Expand Up @@ -689,6 +689,8 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*;
debug_cause_n = DBG_CAUSE_NONE;
debug_mode_n = debug_mode_q;
ctrl_fsm_o.debug_csr_save = 1'b0;
ctrl_fsm_o.debug_trigger_hit = '0; // Mask of which triggers did hit.
ctrl_fsm_o.debug_trigger_hit_update = 1'b0; // Signal that hit bits of mcontrol6 shall be written.
ctrl_fsm_o.block_data_addr = 1'b0;

// Single step halting of IF
Expand Down Expand Up @@ -1130,6 +1132,13 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*;
ctrl_fsm_o.csr_save_cause = !(ebreak_in_wb && debug_mode_q); // No CSR update for ebreak in debug mode
ctrl_fsm_o.debug_csr_save = 1'b1;

// If a trigger was hit, signal that mcontrol6 hit1 and hit0 bits should be written.
// Only triggers configured as mcontrol6 will perform the actual write within debug_triggers.
if (debug_cause_q == DBG_CAUSE_TRIGGER) begin
ctrl_fsm_o.debug_trigger_hit_update = 1'b1;
ctrl_fsm_o.debug_trigger_hit = ex_wb_pipe_i.trigger_match | wpt_match_wb_i;
end

// debug_cause_q set when decision was made to enter debug
if (debug_cause_q != DBG_CAUSE_STEP) begin
// Kill pipeline
Expand Down
10 changes: 6 additions & 4 deletions rtl/cv32e40x_core.sv
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Expand Up @@ -258,7 +258,7 @@ module cv32e40x_core import cv32e40x_pkg::*;
logic lsu_last_op_ex;
lsu_atomic_e lsu_atomic_ex;
mpu_status_e lsu_mpu_status_wb;
logic lsu_wpt_match_wb;
logic [31:0] lsu_wpt_match_wb;
align_status_e lsu_align_status_wb;
logic [31:0] lsu_rdata_wb;
logic [1:0] lsu_err_wb;
Expand All @@ -281,7 +281,7 @@ module cv32e40x_core import cv32e40x_pkg::*;

logic data_stall_wb;

logic wpt_match_wb; // Sticky wpt_match from WB stage
logic [31:0] wpt_match_wb; // Sticky wpt_match from WB stage
mpu_status_e mpu_status_wb; // Sticky mpu_status from WB stage
align_status_e align_status_wb; // Sticky align_status from WB stage

Expand Down Expand Up @@ -310,9 +310,11 @@ module cv32e40x_core import cv32e40x_pkg::*;
dcsr_t dcsr;

// trigger match detected in trigger module (using IF timing)
logic trigger_match_if;
// One bit per trigger (max 32 triggers)
logic [31:0] trigger_match_if;
// trigger match detected in trigger module (using EX/LSU timing)
logic trigger_match_ex;
// One bit per trigger (max 32 triggers)
logic [31:0] trigger_match_ex;
// trigger match detected in trigger module (using WB timing, etrigger)
logic etrigger_wb;

Expand Down
46 changes: 2 additions & 44 deletions rtl/cv32e40x_cs_registers.sv
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Expand Up @@ -109,8 +109,8 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
input logic [31:0] pc_if_i,
input logic ptr_in_if_i,
input privlvl_t priv_lvl_if_i,
output logic trigger_match_if_o,
output logic trigger_match_ex_o,
output logic [31:0] trigger_match_if_o,
output logic [31:0] trigger_match_ex_o,
output logic etrigger_wb_o,
input logic lsu_valid_ex_i,
input logic [31:0] lsu_addr_ex_i,
Expand Down Expand Up @@ -170,15 +170,9 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
logic [31:0] tdata2_rdata;
logic tdata2_we;

logic [31:0] tdata3_rdata;
logic tdata3_we;

logic [31:0] tinfo_rdata;
logic tinfo_we;

logic [31:0] tcontrol_rdata;
logic tcontrol_we;

// Debug
dcsr_t dcsr_q, dcsr_n, dcsr_rdata;
logic dcsr_we;
Expand Down Expand Up @@ -509,15 +503,6 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
end
end

CSR_TDATA3: begin
if (DBG_NUM_TRIGGERS > 0) begin
csr_rdata_int = tdata3_rdata;
end else begin
csr_rdata_int = '0;
illegal_csr_read = 1'b1;
end
end

CSR_TINFO: begin
if (DBG_NUM_TRIGGERS > 0) begin
csr_rdata_int = tinfo_rdata;
Expand All @@ -527,15 +512,6 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
end
end

CSR_TCONTROL: begin
if (DBG_NUM_TRIGGERS > 0) begin
csr_rdata_int = tcontrol_rdata;
end else begin
csr_rdata_int = '0;
illegal_csr_read = 1'b1;
end
end

CSR_DCSR: begin
if (DEBUG) begin
csr_rdata_int = dcsr_rdata;
Expand Down Expand Up @@ -700,12 +676,8 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;

tdata2_we = 1'b0;

tdata3_we = 1'b0;

tinfo_we = 1'b0;

tcontrol_we = 1'b0;

// TODO:XIF add support for SD/XS/FS/VS
mstatus_n = csr_next_value(mstatus_t'{
tw: 1'b0,
Expand Down Expand Up @@ -975,20 +947,10 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
end
end

CSR_TDATA3: begin
if (ctrl_fsm_i.debug_mode) begin
tdata3_we = 1'b1;
end
end

CSR_TINFO: begin
tinfo_we = 1'b1;
end

CSR_TCONTROL: begin
tcontrol_we = 1'b1;
end

CSR_DCSR: begin
dcsr_we = 1'b1;
end
Expand Down Expand Up @@ -1628,17 +1590,13 @@ dcsr_we = 1'b1;
.tselect_we_i ( tselect_we ),
.tdata1_we_i ( tdata1_we ),
.tdata2_we_i ( tdata2_we ),
.tdata3_we_i ( tdata3_we ),
.tinfo_we_i ( tinfo_we ),
.tcontrol_we_i ( tcontrol_we ),

// CSR read data outputs
.tselect_rdata_o ( tselect_rdata ),
.tdata1_rdata_o ( tdata1_rdata ),
.tdata2_rdata_o ( tdata2_rdata ),
.tdata3_rdata_o ( tdata3_rdata ),
.tinfo_rdata_o ( tinfo_rdata ),
.tcontrol_rdata_o ( tcontrol_rdata ),

// IF stage inputs
.pc_if_i ( pc_if_i ),
Expand Down