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Lint cleanup #875

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merged 1 commit into from Jun 21, 2023
Merged

Lint cleanup #875

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4 changes: 2 additions & 2 deletions rtl/cv32e40x_alignment_buffer.sv
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Expand Up @@ -129,12 +129,12 @@ module cv32e40x_alignment_buffer import cv32e40x_pkg::*;
(outstanding_cnt_q < 2) &&
!(ptr_fetch_accepted_q && !ctrl_fsm_i.pc_set) && // No fetch until next pc_set after accepted pointer fetches
(((instr_cnt_q - pop_q) == 'd0) ||
((instr_cnt_q - pop_q) == 'd1 && outstanding_cnt_q == 2'd0) ||
((instr_cnt_q - pop_q) == 'd1 && outstanding_cnt_q == ALBUF_CNT_WIDTH'(0)) ||
ctrl_fsm_i.pc_set);


// Busy if we expect any responses, or we have an active fetch_valid_o
assign prefetch_busy_o = (outstanding_cnt_q != 3'b000)|| fetch_valid_o;
assign prefetch_busy_o = (outstanding_cnt_q != ALBUF_CNT_WIDTH'(0))|| fetch_valid_o;

// Indicate that there will be one pending transaction in the next cycle
assign one_txn_pend_n = outstanding_cnt_n == ALBUF_CNT_WIDTH'(1);
Expand Down
2 changes: 1 addition & 1 deletion rtl/cv32e40x_controller_fsm.sv
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Expand Up @@ -596,7 +596,7 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*;
// Mux used to select PC from the different pipeline stages
always_comb begin

ctrl_fsm_o.pipe_pc = PC_WB;
ctrl_fsm_o.pipe_pc = ex_wb_pipe_i.pc;

unique case (pipe_pc_mux_ctrl)
PC_WB: ctrl_fsm_o.pipe_pc = ex_wb_pipe_i.pc;
Expand Down
12 changes: 9 additions & 3 deletions rtl/cv32e40x_core.sv
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Expand Up @@ -355,6 +355,8 @@ module cv32e40x_core import cv32e40x_pkg::*;
// eXtension interface signals
logic xif_offloading_id;

logic unused_signals;

// Internal OBI interfaces
cv32e40x_if_c_obi #(.REQ_TYPE(obi_inst_req_t), .RESP_TYPE(obi_inst_resp_t)) m_c_obi_instr_if();
cv32e40x_if_c_obi #(.REQ_TYPE(obi_data_req_t), .RESP_TYPE(obi_data_resp_t)) m_c_obi_data_if();
Expand Down Expand Up @@ -482,7 +484,7 @@ module cv32e40x_core import cv32e40x_pkg::*;
.mtvt_addr_i ( mtvt_addr ), // CLIC vector base
.jvt_mode_i ( jvt_mode ),

.m_c_obi_instr_if ( m_c_obi_instr_if ), // Instruction bus interface
.m_c_obi_instr_if ( m_c_obi_instr_if.master ), // Instruction bus interface

.if_id_pipe_o ( if_id_pipe ),

Expand Down Expand Up @@ -674,7 +676,7 @@ module cv32e40x_core import cv32e40x_pkg::*;
.ctrl_fsm_i ( ctrl_fsm ),

// Data OBI interface
.m_c_obi_data_if ( m_c_obi_data_if ),
.m_c_obi_data_if ( m_c_obi_data_if.master ),

// Control signals
.busy_o ( lsu_busy ),
Expand Down Expand Up @@ -991,7 +993,7 @@ module cv32e40x_core import cv32e40x_pkg::*;
.fencei_flush_req_o ( fencei_flush_req_o ),

// Data OBI interface
.m_c_obi_data_if ( m_c_obi_data_if ),
.m_c_obi_data_if ( m_c_obi_data_if.monitor),

.id_ready_i ( id_ready ),
.id_valid_i ( id_valid ),
Expand Down Expand Up @@ -1131,4 +1133,8 @@ module cv32e40x_core import cv32e40x_pkg::*;
.we_i ( rf_we )
);


// Some signals are unused on purpose (typically they are used by RVFI code). Use them here for easier LINT waiving.
assign unused_signals = dbg_ack | irq_ack | (|irq_id) | (|irq_level) | (|irq_priv) | irq_shv;

endmodule
15 changes: 8 additions & 7 deletions rtl/cv32e40x_cs_registers.sv
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Expand Up @@ -1779,7 +1779,7 @@ dcsr_we = 1'b1;
!mcountinhibit_rdata[wcnt_gidx] &&
!debug_stopcount &&
hpm_events[1];
end else if( (wcnt_gidx>2) && (wcnt_gidx<(NUM_MHPMCOUNTERS+3))) begin : gen_mhpmcounter
end else if( (wcnt_gidx>2) && (wcnt_gidx<(NUM_MHPMCOUNTERS+3))) begin : gen_mhpmcounter_write_increment
// add +1 if any event is enabled and active
assign mhpmcounter_write_increment[wcnt_gidx] = !mhpmcounter_write_lower[wcnt_gidx] &&
!mhpmcounter_write_upper[wcnt_gidx] &&
Expand All @@ -1805,7 +1805,7 @@ dcsr_we = 1'b1;
// Programable HPM counters start at index 3
if( (nxt_gidx == 1) ||
(nxt_gidx >= (NUM_MHPMCOUNTERS+3) ) )
begin : gen_non_implemented
begin : gen_non_implemented_nextvalue
assign mhpmcounter_n[nxt_gidx] = 'b0;
assign mhpmcounter_we[nxt_gidx] = 2'b0;
end
Expand Down Expand Up @@ -1837,10 +1837,10 @@ dcsr_we = 1'b1;
// Programable HPM counters start at index 3
if( (cnt_gidx == 1) ||
(cnt_gidx >= (NUM_MHPMCOUNTERS+3) ) )
begin : gen_non_implemented
begin : gen_non_implemented_mhpmcounter
assign mhpmcounter_q[cnt_gidx] = 'b0;
end
else begin : gen_implemented
else begin : gen_implemented_mhpmcounter
always_ff @(posedge clk, negedge rst_n)
if (!rst_n) begin
mhpmcounter_q[cnt_gidx] <= 'b0;
Expand All @@ -1864,10 +1864,10 @@ dcsr_we = 1'b1;
// programable HPM events start at index3
if( (evt_gidx < 3) ||
(evt_gidx >= (NUM_MHPMCOUNTERS+3) ) )
begin : gen_non_implemented
begin : gen_non_implemented_mhpmevent
assign mhpmevent_q[evt_gidx] = 'b0;
end
else begin : gen_implemented
else begin : gen_implemented_mhpmevent
if (NUM_HPM_EVENTS < 32) begin : gen_tie_off
assign mhpmevent_q[evt_gidx][31:NUM_HPM_EVENTS] = 'b0;
end
Expand Down Expand Up @@ -1903,6 +1903,7 @@ dcsr_we = 1'b1;
assign unused_signals = mstatush_we | misa_we | mip_we | mvendorid_we |
marchid_we | mimpid_we | mhartid_we | mconfigptr_we | mtval_we | (|mnxti_n) | mscratchcsw_we | mscratchcswl_we |
(|mscratchcsw_rdata) | (|mscratchcswl_rdata) | (|mscratchcsw_n) | (|mscratchcswl_n) |
mscratchcsw_in_wb | mscratchcswl_in_wb | mnxti_in_wb;
mscratchcsw_in_wb | mscratchcswl_in_wb | mnxti_in_wb |
(|mtval_n) | (|mconfigptr_n) | (|mhartid_n) | (|mimpid_n) | (|marchid_n) | (|mvendorid_n) | (|mip_n) | (|misa_n) | (|mstatush_n);

endmodule
4 changes: 2 additions & 2 deletions rtl/cv32e40x_ff_one.sv
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Expand Up @@ -58,15 +58,15 @@ module cv32e40x_ff_one
for (level = 0; level < NUM_LEVELS; level++) begin : gen_tree
//------------------------------------------------------------
if (level < NUM_LEVELS-1) begin : gen_non_root_level
for (l = 0; l < 2**level; l++) begin : gen_node
for (l = 0; l < 2**level; l++) begin : gen_node_non_root
assign sel_nodes[2**level-1+l] = sel_nodes[2**(level+1)-1+l*2] | sel_nodes[2**(level+1)-1+l*2+1];
assign index_nodes[2**level-1+l] = (sel_nodes[2**(level+1)-1+l*2] == 1'b1) ?
index_nodes[2**(level+1)-1+l*2] : index_nodes[2**(level+1)-1+l*2+1];
end
end
//------------------------------------------------------------
if (level == NUM_LEVELS-1) begin : gen_root_level
for (k = 0; k < 2**level; k++) begin : gen_node
for (k = 0; k < 2**level; k++) begin : gen_node_root
// if two successive indices are still in the vector...
if (k * 2 < LEN-1) begin : gen_two
assign sel_nodes[2**level-1+k] = in_i[k*2] | in_i[k*2+1];
Expand Down
2 changes: 0 additions & 2 deletions rtl/cv32e40x_load_store_unit.sv
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Expand Up @@ -109,7 +109,6 @@ module cv32e40x_load_store_unit import cv32e40x_pkg::*;
// Align_check transaction request (to cv32e40x_align_check)
logic alcheck_trans_valid;
logic alcheck_trans_ready;
logic alcheck_trans_pushpop;
obi_data_req_t alcheck_trans;

// Transaction request to cv32e40x_mpu
Expand All @@ -131,7 +130,6 @@ module cv32e40x_load_store_unit import cv32e40x_pkg::*;

// Transaction response interface (from cv32e40x_align_check)
logic alcheck_resp_valid;
logic [31:0] alcheck_resp_rdata;
data_resp_t alcheck_resp;

// Transaction response interface (from cv32e40x_mpu)
Expand Down
1 change: 0 additions & 1 deletion rtl/cv32e40x_mpu.sv
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Expand Up @@ -82,7 +82,6 @@ module cv32e40x_mpu import cv32e40x_pkg::*;
logic core_trans_we;
logic instr_fetch_access;
logic load_access;
logic wpt_match;
logic core_trans_debug_region;

// Detect a debug mode transaction to the Debug Module region
Expand Down
8 changes: 4 additions & 4 deletions rtl/cv32e40x_sequencer.sv
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Expand Up @@ -307,7 +307,7 @@ module cv32e40x_sequencer import cv32e40x_pkg::*;
end
end else if (seq_move_a2s) begin
// addi s*, a0, 0
instr_o.bus_resp.rdata = {12'h000, 5'd10, 3'b000, sn_to_regnum(5'(instr[9:7])), OPCODE_OPIMM};
instr_o.bus_resp.rdata = {12'h000, 5'd10, 3'b000, sn_to_regnum({2'h0,instr[9:7]}), OPCODE_OPIMM};
seq_state_n = S_DMOVE;
end else if (seq_tbljmp_o) begin
if (instr[9:7] == 3'b000) begin
Expand All @@ -323,7 +323,7 @@ module cv32e40x_sequencer import cv32e40x_pkg::*;
end else if (seq_move_s2a) begin
// move s to a
// addi a0, s*, 0
instr_o.bus_resp.rdata = {12'h000, sn_to_regnum(5'(instr[9:7])), 3'b000, 5'd10, OPCODE_OPIMM};
instr_o.bus_resp.rdata = {12'h000, sn_to_regnum({2'h0,instr[9:7]}), 3'b000, 5'd10, OPCODE_OPIMM};
seq_state_n = S_DMOVE;
end

Expand Down Expand Up @@ -352,10 +352,10 @@ module cv32e40x_sequencer import cv32e40x_pkg::*;
// Second half of double moves
if (seq_move_a2s) begin
// addi s*, a1, 0
instr_o.bus_resp.rdata = {12'h000, 5'd11, 3'b000, sn_to_regnum(5'(instr[4:2])), OPCODE_OPIMM};
instr_o.bus_resp.rdata = {12'h000, 5'd11, 3'b000, sn_to_regnum({2'h0,instr[4:2]}), OPCODE_OPIMM};
end else begin
// addi a1, s*, 0
instr_o.bus_resp.rdata = {12'h000, sn_to_regnum(5'(instr[4:2])), 3'b000, 5'd11, OPCODE_OPIMM};
instr_o.bus_resp.rdata = {12'h000, sn_to_regnum({2'h0,instr[4:2]}), 3'b000, 5'd11, OPCODE_OPIMM};
end

seq_state_n = S_IDLE;
Expand Down
2 changes: 1 addition & 1 deletion rtl/cv32e40x_wb_stage.sv
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Expand Up @@ -178,7 +178,7 @@ module cv32e40x_wb_stage import cv32e40x_pkg::*;

// Append any MPU exception to abort_op
// An abort_op_o = 1 will terminate a sequence, either to take an exception or debug due to trigger match.
assign abort_op_o = ex_wb_pipe_i.abort_op || ( ex_wb_pipe_i.lsu_en && lsu_exception) || (ex_wb_pipe_i.lsu_en && lsu_wpt_match);
assign abort_op_o = ex_wb_pipe_i.abort_op || ( ex_wb_pipe_i.lsu_en && lsu_exception) || (ex_wb_pipe_i.lsu_en && |lsu_wpt_match);

// Export signal indicating WB stage stalled by load/store
assign data_stall_o = ex_wb_pipe_i.lsu_en && !lsu_valid && instr_valid;
Expand Down